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33,057 Commits 71 Branches 509 Tags 780 MiB
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33057 Commits

Author SHA1 Message Date
Michael du Breuil 1183ed61fb AP_HAL: Remove timer process suspension interface 2018-06-06 07:16:58 +10:00
Michael du Breuil c4a66349ef DataFlash: Remove suspend timer calls, restirct flush() to replay 2018-06-06 07:16:58 +10:00
Andrew Tridgell 1ed6a9d34b HAL_ChibiOS: added MCU tables for STM32F777 2018-06-06 07:15:41 +10:00
Andrew Tridgell d1caa86e12 HAL_ChibiOS: adjust DMA priorities for fmuv3 2018-06-06 07:15:41 +10:00
Andrew Tridgell c0e8114f9a AP_BLHeli: removed extra UDID_START define 2018-06-06 07:15:41 +10:00
Andrew Tridgell c273b23940 HAL_ChibiOS: moved MCU config to python database 
this moves the key MCU config variables related to memory to the
python MCU database, allowing the hwdef.dat to be considerably simpler
 2018-06-06 07:15:41 +10:00
Andrew Tridgell f390e35c99 HAL_ChibiOS: use port_disable in reboot 
this provides a more reliable way to stop all interrupts
 2018-06-06 07:15:41 +10:00
Andrew Tridgell a1c97d0585 HAL_ChibiOS: disable paranoid checks for fmuv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell a945c97ec6 HAL_ChibiOS: fixed 3-way DMA sharing bug 
when we have 3 way contention across two DMA streams we could get the
dma_deallocate function called in an object from two places at
once. This adds a mutex that prevents that scenario
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 0e09dc75c0 HAL_ChibiOS: flush all memory on chSysHalt() 
this makes debugging a lot easier, as gdb can see the values in dcache
 2018-06-06 07:15:41 +10:00
Andrew Tridgell dc2a776985 AP_GPS: fixed fake ublox 3D lock PVT speed accuracy 
allows EKF to startup fully with fake GPS lock
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 2493cdbcb6 HAL_ChibiOS: switch to new bouncebuffer system 
this removes the dma_flush and dma_invalidate methods and uses a
common bouncebuffer system for all CPU types. This enables microSD
support on STM32F7
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 0b1e26a470 HAL_ChibiOS: added bouncebuffer system 
this makes our bouncebuffers available for ChibiOS system
drivers. This is needed for SDMMCv1 on STM32F7
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 04774d309c ChibiOS: submodule update 
use bouncebuffer for SDMMCv1
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 56ce3f057d HAL_ChibiOS: added DRDY and SDMMC pins for FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell 018c9ad40b HAL_ChibiOS: fixed build warnings 2018-06-06 07:15:41 +10:00
Andrew Tridgell f25b95f287 HAL_ChibiOS: fixed array length in ADC debug code 2018-06-06 07:15:41 +10:00
Andrew Tridgell fef1b0ffc6 HAL_ChibiOS: fixed I2C flush/invalidate calls 2018-06-06 07:15:41 +10:00
Andrew Tridgell 0fade4eb9e HAL_ChibiOS: make sure the UART bounce buffers are DMA safe 2018-06-06 07:15:41 +10:00
Andrew Tridgell eec4a12cc2 HAL_ChibiOS: switched to using DTCM memory for DMA 
this uses SRAM1 and SRAM2 for main memory, which enables the use of the
data cache for faster operation, and using DTCM for all DMA operations.
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 8b1db792ee HAL_ChibiOS: ensure ADC memory is aligned for DMA access 2018-06-06 07:15:41 +10:00
Andrew Tridgell bb2e7a189f HAL_ChibiOS: added a debug function for showing stack free 
this can be enabled when needed to investigate stack space remaining
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 010cd71ab6 HAL_ChibiOS: enable CAN on FMUv5 
and fixed voltage scaling defaults
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 2087354939 HAL_ChibiOS: align buffers to STM32F7 cache lines 
this allows for DMA flush and invalidate operations to work on all
dynamically allocated memory
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 762e4f9915 HAL_ChibiOS: fixed dma priorities for fmuv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell 77d95f6744 HAL_ChibiOS: fmuv5 tweaks 2018-06-06 07:15:41 +10:00
Andrew Tridgell a220220758 HAL_ChibiOS: added comment on IS_DMA_SAFE() 2018-06-06 07:15:41 +10:00
Andrew Tridgell 4d4ea894e8 HAL_ChibiOS: disable i2c device debug code 2018-06-06 07:15:41 +10:00
Andrew Tridgell 11b327e336 scripts: update decode_devid.py for new IMUs 2018-06-06 07:15:41 +10:00
Andrew Tridgell edb831653f HAL_ChibiOS: added dma_flush and dma_invalidate operations 
these are needed to manage the data cache on the STM32F7
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 7449e15313 HAL_ChibiOS: disable flash storage option on FMUv5 
F7 flash driver not working yet
 2018-06-06 07:15:41 +10:00
Andrew Tridgell b961e12456 HAL_ChibiOS: support having no flash storage option 2018-06-06 07:15:41 +10:00
Andrew Tridgell 2d8748ddce HAL_ChibiOS: enable ADCs and buzzer for fmuv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell 6aab9232ef HAL_ChibiOS: enable aux pwm channels on FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell 3242b5eeb9 AP_IOMCU: fail to boot if IO firmware CRC and update fails 
we don't want to fly with a bad IO firmware
 2018-06-06 07:15:41 +10:00
Andrew Tridgell 677b5f94b2 AP_BoardConfig: allow for non-bool BRD_IO_ENABLE 
this will be used to avoid CRC checks for IO fw development testing
 2018-06-06 07:15:41 +10:00
Andrew Tridgell db9bf19e46 HAL_ChibiOS: enable i2c for FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell 99540a184c AP_Compass: enable FMUv5 compass 2018-06-06 07:15:41 +10:00
Andrew Tridgell 77bb69fa2e HAL_ChibiOS: enabled UARTs for FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell ac44189ab2 HAL_ChibiOS: setup two IMUs for FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell ccdfc75dd9 AP_Compass: placeholder for FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell bfa66c9397 AP_InertialSensor: detect two IMUs on FMUv5 2018-06-06 07:15:41 +10:00
Andrew Tridgell 0047807fbf AP_IOMCU: fixed build error on F7 2018-06-06 07:15:41 +10:00
Andrew Tridgell 721f3cd5d1 HAL_ChibiOS: fixed flash layout for F7 
thanks to @alielectric
 2018-06-06 07:15:41 +10:00
Andrew Tridgell ae1a58ecb8 AP_Baro: added FMUv5 support 2018-06-06 07:15:41 +10:00
Andrew Tridgell 751f290be6 AP_BoardConfig: setup FMUv5 for board detection 2018-06-06 07:15:41 +10:00
Andrew Tridgell 01f5d1a17c HAL_ChibiOS: first IMU working 2018-06-06 07:15:41 +10:00
Andrew Tridgell eca634ec62 HAL_ChibiOS: support 6 SPI buses 2018-06-06 07:15:41 +10:00
Andrew Tridgell 4ad757b4d1 HAL_ChibiOS: fixed pincount for F7 2018-06-06 07:15:41 +10:00
Andrew Tridgell 876899c48d HAL_ChibiOS: baro and FRAM working for fmuv5 2018-06-06 07:15:41 +10:00