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HAL_ChibiOS: setup two IMUs for FMUv5

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This commit is contained in:
Andrew Tridgell 2018-05-29 21:49:58 +10:00
parent ccdfc75dd9
commit ac44189ab2
1 changed files with 17 additions and 4 deletions
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21
libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat
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@ -17,6 +17,7 @@ define STM32_PLLP_VALUE 2
define STM32_PLLQ_VALUE 9
define CONFIG_HAL_BOARD_SUBTYPE HAL_BOARD_SUBTYPE_CHIBIOS_FMUV5
define HAL_CHIBIOS_ARCH_FMUV5 1
# board ID for firmware load
APJ_BOARD_ID 50
@ -81,9 +82,20 @@ PG5 VDD_5V_RC_EN OUTPUT HIGH
PG6 VDD_5V_WIFI_EN OUTPUT HIGH
PG7 VDD_3V3_SD_CARD_EN OUTPUT HIGH
# now the 2nd GPS UART
# UART8 serial4 GPS2
#PE0 UART8_RX UART8
#PE1 UART8_TX UART8
# UART for IOMCU
#IOMCU_UART UART8
# enable SBUS_OUT on IOMCU (if you have an IOMCU)
define AP_FEATURE_SBUS_OUT 1
SPIDEV ms5611 SPI4 DEVID1 MS5611_CS MODE3 20*MHZ 20*MHZ
SPIDEV mpu6000 SPI1 DEVID1 ICM20689_CS MODE0 1*MHZ 1*MHZ
SPIDEV icm20602 SPI1 DEVID2 ICM20602_CS MODE0 1*MHZ 1*MHZ
SPIDEV icm20689 SPI1 DEVID1 ICM20689_CS MODE0 1*MHZ 8*MHZ
SPIDEV icm20602 SPI1 DEVID2 ICM20602_CS MODE0 1*MHZ 8*MHZ
SPIDEV bmi055_g SPI1 DEVID3 BMI055_G_CS MODE3 8*MHZ 8*MHZ
SPIDEV bmi055_a SPI1 DEVID4 BMI055_A_CS MODE3 8*MHZ 8*MHZ
SPIDEV ramtron SPI2 DEVID1 FRAM_CS MODE3 8*MHZ 8*MHZ
@ -92,10 +104,9 @@ SPIDEV ramtron SPI2 DEVID1 FRAM_CS MODE3 8*MHZ 8*MHZ
define HAL_STORAGE_SIZE 16384
define HAL_WITH_RAMTRON 1
define STORAGE_FLASH_PAGE 7
define STORAGE_FLASH_PAGE 11
define HAL_BARO_DEFAULT HAL_BARO_MS5611_SPI
define HAL_INS_DEFAULT HAL_INS_MPU60XX_SPI
define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE
@ -105,3 +116,5 @@ define CH_DBG_SYSTEM_STATE_CHECK TRUE
define CH_DBG_ENABLE_STACK_CHECK TRUE
# define HAL_SPI_CHECK_CLOCK_FREQ 1
ROMFS io_firmware.bin Tools/IO_Firmware/fmuv2_IO.bin