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25 Commits

Author SHA1 Message Date
Peter Barker 139c460fa5 hwdef: remove unused define NO_DATAFLASH 2021-11-24 18:18:06 +11:00
bugobliterator 8651d99de6 HAL_ChibiOS: move to using parameter STORAGE_FLASH_PAGE instead of define 2021-10-30 19:24:57 +11:00
Andrew Tridgell 80836ca1d9 HAL_ChibiOS: simplify AP_Periph hwdef.dat 2021-10-26 15:56:53 +11:00
Andrew Tridgell 68146d541c HAL_ChibiOS: removed boilerplate lines from bootloaders 2021-10-26 15:56:53 +11:00
Andrew Tridgell 822e657a70 HAL_ChibiOS: increase PROCESS_STACK on several boards 
use min of 0xA00 for AP_Periph. A larger stack is needed for parameter
fetching
 2021-10-20 19:06:35 +11:00
Peter Barker 1bd62362a4 AP_HAL_ChibiOS: move from HAL_NO_GCS to HAL_GCS_ENABLED 2021-09-22 21:37:00 +10:00
Andrew Tridgell a098c80671 HAL_ChibiOS: use DNA for node allocation on Matek GPS 
this works as MSP is now active when a DNA server is not found
 2021-07-15 14:38:11 +10:00
Peter Barker 31ef6db937 AP_HAL_ChibiOS: remove redundant HAL_LOGGING_ENABLED from AP_Periph hwdefs 2021-05-19 17:38:47 +10:00
Peter Barker 7d8c5757d6 AP_HAL_ChibiOS: move from HAL_NO_LOGGING to HAL_LOGGING_ENABLED 2021-05-19 17:38:47 +10:00
Andy Piper f9c5f9be00 AP_HAL_ChibiOS: make dshot DMA unlock event driven in order to allow unlocking from rcout thread 
refactor rcout into separate thread and process all dshot requests there
move uart DMA completion to event model
process dshot locks in strick reverse order when unlocking
convert Shared_DMA to use mutexes
move UART transmit to a thread-per-uart
do blocking UART DMA transactions
do blocking dshot DMA transactions
trim stack sizes
cancel dma transactions on dshot when timeout occurs
support contention stats on blocking locking
move thread supression into chibios_hwdef.py
invalidate DMA bounce buffer correctly
separate UART initialisation into two halves
cleanup UART transaction timeouts
add @SYS/uarts.txt
move half-duplex handling to TX thread
correct thread statistics after use of ExpandingString
set unbuffered TX thread priority owner + 1
correctly unlock serial_led_send()
don't share IMU RX on KakuteF7Mini
observe dshot pulse time more accurately.
set TRBUFF bit for UART DMA transfers
deal with UART DMA timeouts correctly
don't deadlock on reverse ordered DMA locks
change PORT_INT_REQUIRED_STACK to 128
 2021-02-20 14:37:11 +11:00
mateksys 97c2b7228e AP_Periph: Matek F303 and F405 AP_Periph use DSP310 baro 2021-02-18 11:51:50 +11:00
Andrew Tridgell d81c2ee407 HAL_ChibiOS: allow for some embedded parameters on AP_Periph builds 2021-01-21 06:19:46 +11:00
Andrew Tridgell e260c7ad59 HAL_ChibiOS: update f303-MatekGPS to allow disable of MSP 
and use DMA for MSP
 2021-01-01 15:40:13 +11:00
Tom Pittenger f670f7a9b6 AP_HAL_ChibiOS: change ADSB to use param ADSB_PORT instead of define 2020-12-17 23:24:04 -08:00
Andrew Tridgell e54fc4b0de AP_HAL_ChibiOS: convert to using hal.serial() instead of hal.uartX 2020-12-15 10:32:46 +11:00
Tom Pittenger 2203bf2400 AP_HAL_ChibiOS: Add f303-periph default RANGEFINDER_MAX_INSTANCES 1 2020-12-09 18:05:24 +11:00
Andrew Tridgell cf22caa7ef HAL_ChibiOS: raise stack limits in f303 peripherals 2020-12-01 11:14:50 +11:00
Andrew Tridgell 573cd6db6d HAL_ChibiOS: adjust MAIN_STACK for more ISR stack 
we need more stack to deal with interrupt nesting between CAN, system
timer and serial interrupts
 2020-12-01 11:14:50 +11:00
Andrew Tridgell a587195912 HAL_ChibiOS: change f303-MatekGPS to 5Hz by default 2020-11-27 19:41:33 +11:00
Andrew Tridgell 0e8c8c29a8 HAL_ChibiOS: fixed f303-MatekGPS build 2020-09-24 12:32:19 +10:00
Andrew Tridgell 90e488d29d HAL_ChibiOS: set airspeed type in f303-MatekGPS fw 2020-09-09 12:04:49 +10:00
Andrew Tridgell e95a44e73c HAL_ChibiOS: run f303-MatekGPS at 10Hz 2020-09-09 06:35:50 +10:00
Andrew Tridgell 844db20db0 HAL_ChibiOS: use a default node ID for f303-MatekGPS 2020-09-09 06:35:50 +10:00
Andrew Tridgell 9c7568eb5f HAL_ChibiOS: enable MSP output for f303-MatekGPS 2020-09-09 06:35:50 +10:00
Andrew Tridgell 36442dc9b0 HAL_ChibiOS: added Matek CAN GPS 
supports GPS, baro, mag and airspeed
 2020-08-25 09:59:15 +10:00