this avoids an issue with the ChibiOS 20.3 virtual timer
implementation that can result in a scheduling slip equal to the
system timer period.
Andy has been suggesting this change for a while. I resisted it as I
thought it would impact on soft-serial parsing, but it turns out it
doesn't.
Fixes issue #18383
The 100Hz update rate means there is a significant chance of an arming
failure after mission upload if you try to arm shortly after the
update.
Each mission item is 15 bytes, so with a 1200 item mission we need to
write 18000 bytes to storage. At 100Hz, with 8 bytes per storage line,
that takes over 22 seconds.
refactor rcout into separate thread and process all dshot requests there
move uart DMA completion to event model
process dshot locks in strick reverse order when unlocking
convert Shared_DMA to use mutexes
move UART transmit to a thread-per-uart
do blocking UART DMA transactions
do blocking dshot DMA transactions
trim stack sizes
cancel dma transactions on dshot when timeout occurs
support contention stats on blocking locking
move thread supression into chibios_hwdef.py
invalidate DMA bounce buffer correctly
separate UART initialisation into two halves
cleanup UART transaction timeouts
add @SYS/uarts.txt
move half-duplex handling to TX thread
correct thread statistics after use of ExpandingString
set unbuffered TX thread priority owner + 1
correctly unlock serial_led_send()
don't share IMU RX on KakuteF7Mini
observe dshot pulse time more accurately.
set TRBUFF bit for UART DMA transfers
deal with UART DMA timeouts correctly
don't deadlock on reverse ordered DMA locks
change PORT_INT_REQUIRED_STACK to 128
this prevents an occasional boot hang on systems with DShot
enabled. We shouldn't be starting DShot output till after setup() is
complete as the outputs are still being configured
the STM32H7 has 64k of ITCM memory at address zero. We allow
allocation of everything except the first 1024 bytes. This checks for
those reserved bytes being overwritte, which would indicate a write to
nullptr
This implements a max quota of GPIO interrupts per 100ms period to
prevent high interrupt counts from consuming all CPU and causing a
lockup. The limit is set as 10k interrupts per 0.1s period. That limit
should be high enough for all reasonable uses of GPIO interrupt
handlers while being below the level that causes significant CPU loads
and flight issues
This addresses issue #15384
Andrew Tridgell
Peter Barker
Andy Piper
Siddharth Purohit
Stephen Dade
Mirko Denecke
Tom Pittenger
Michael du Breuil