The ADC peripheral can only support up to
50MHz on rev V silicon and 36MHz on Y silicon.
The existing driver always used no prescaler
and kept boost setting at 0.
nxp/rt117x:Fix Pin IRQ
nxp/rt117x:Support 4 i2c busses
nxp/rt117x:Add px4io_serial support
nxp/imxrt:Expand ToneAlarmInterface to GPT 3 & 4
px4_fmu-6xrt:Using imxrt_flexspi_nor_octal
px4_fmu-6xrt:Entry is start
px4_fmu-6xrt:Add Proper MTD
px4_fmu-6xrt:Set I2C Buses
px4_fmu-6xrt:Proper SPI usage
px4_fmu-6xrt:Adjust memory Map to use the 2 MB
px4_fmu-6xrt:Bring in ROMAPI
px4_fmu-6xrt:Push FLASH to 200Mhz
px4_fmu-6xrt:Use BOARD_I2C_LATEINIT
px4_fmu-6xrt:Clock Config remove unused devices
px4_fmu-6xrt:Remove EVK SDRAM IO
px4_fmu-6xrt:Enable SE550 using HW_VER_REV_DRIVE
px4_fmu-6xrt:Use MTD to mount FRAM on Flex SPI
px4_fmu-6xrt:Manifest
px4_fmu-6xrt:Restore board_peripheral_reset
px4_fmu-6xrt:Set I2C buss Interna/Externa and startup
nxp/rt117x:Set 6 I2C busses
px4_fmu-6xrt:Correct Clock Sources and Freqency Settings
px4_fmu-6xrt:Correct ADC Settings
px4_fmu-6xrt:Tune FlexSPI config and sync header with debug variant Linker prep for rodata ahb partitioning
px4_fmu-6xrt:FlexSPI prefetch partition split .text and .rodata
Current config
1KB Prefetch .rodata
3KB Prefetch .text
px4_fmu-6xrt:Run imxrt_flash_setup_prefetch_partition from ram with barriers
px4_fmu-6xrt:Use All OCTL setting from FLASH g_flash_config SANS lookupTable
px4_fmu-6xrt:Octal spi boot/debug problem bypass
px4_fmu-6xrt:Add PWM test
px4_fmu-6xrt:Fix clockconfig and USB vbus sense
px4_fmu-6xrt: Use TCM
px4_fmu-6xrt: Ethernet bringup
imxrt: use unique_id register for board_identity
px4_fmu-6xrt: update ITCM mapping, todo proper trap on pc hitting 0x0
px4_fmu-6xrt:correct rotation icm42688p onboard imu
rt117x: Add SSARC HP RAM driver for memory dumps
px4_fmu-6xrt: Enable hardfault_log
px4_fmu-6xrt: Enable DMA pool
px4_fmu-6xrt: fix uart mapping
px4_fmu-6xrt: enable SocketCAN & DroneCAN
px4_fmu-6xrt:Command line history TAB completion
px4_fmu-6xrt:Fix pinning duplication
px4_fmu-6xrt:Support conditional PHY address based on selected PHY
px4_fmu-6xrt:Add Pull Downs on CTS, use GPIO for RTS
px4_fmu-6xrt:Set TelemN TX Slew rate and Drive Strenth to max
px4_fmu-6xrt::Set TELEM Buffers add HW HS
px4_fmu-6xrt:Turn off DMA poll
px4_fmu-6xrt:RC_SERIAL_PORT needed to be px4io to disable rc_input using TELEM2!
px4_fmu-6xrt: bootloader (#22228)
* imxrt:Add bootloader support
* bootloader:imxrt clear BOOT_RTC_SIGNATURE
* px4_fmu-6xrt:Add bootloader
* px4_fmu-6xrt:bootloader removed ADC
* px4_fmu-6xrt:bootloader base bootloader script off of script.ld
* px4_fmu-6xrt:add _bootdelay_signature & change entry from 0x30000000 to 0x30040000
* px4_fmu-6xrt:hw_config Bootloader has to have 12 bytes
px4_fmu-6xrt:Default to use LAN8742A PHY
px4_fmu-v6xrt:VID Set to Drone Code
board_reset:Enable ability to write RTC GP regs
px4_fmu-6xrt:Fix CMP0079 error
rt117x:micro_hal Add a PX4_MAKE_GPIO_PULLED_INPUT
px4_fmu-v6xrt:Set CTS High before VDD_5V applided to ports to avoid radios fro entering bootloaders
fmu-v6xrt: increase 5v down time
fmu-v6xrt:Ready for Release DEBUGASSERTS off and Console 57600,
Bootloder updated.
imxrt:board_hw_rev_ver Rework for 3.893V Ref
px4_fmu-v6xrt:Move ADC to Port3
imxrt:117x Reuse all but io_timer_hw_description and imxrt_pinirq.c
imxrt:ADC & LPADC bifurcation and restructuring
imxrt:hrt support Up to GPT6
nxp/rt117x:adc Corrected
The UART7 TXDMA services TELEM1 with flow control. If CTS is high, the
transmitting thread will wait on a semaphore, which may block other
threads from acquiring necessary resources to make progress, for
example, preventing MAVLINK instances from transmitting.
This change in NuttX makes the TXDMA acquire the semaphore in a
non-blocking way, preventing this issue.
We provide a latency measurement in the input capture handler.
However, since the timer was not enabled, none of the counter were
running therefore all counters were zero, thus latency was also zero.
Since the HRT is used to provide a timestamp, the lack of the running
timer was never noticed. After enabling the timer, latency now correctly
shows 9-10 counts.
Events have a global, system-wide sequence number, which must be handled
atomically, (fetching and incrementing the sequence AND sending the event
to uORB must be atomic). Currently in FLAT mode, only one instance of this
sequence number exists, so it is OK to have it in px4_platform.
However, in PROTECTED mode px4_platform is instantiated both in kernel-
and user spaces, which makes two instances of this sequence number, which
causes problems in the mavlink event handling logic.
When mavlink receives and handles events, it expects that:
- The sequence numbers arrive in order (seq n is followed by n+1 etc)
- It increments by 1
- There is only one instance of the sequence number
In PROTECTED mode this is violated, as the kernel and user sequence
numbers run freely on their own. This patch fixes the issue by moving
the event backend to the kernel and by providing user access to it via
ioctl.
c23b72dffe [BACKPORT] sched/semaphore: Remove restriction to use nxsem_trywait from ISR
fd47cd20a2 [BACKPORT] imxrt:Serial Preserve all but W1C bit in SR
c55f0fd3ac [BACKPORT] imxrt: lpspi dma invalidate cache after exchange
198c7caecb [BACKPORT] imxrt:lpi2c fix status handeling & race
cbd2e44c10 [BACKPORT] s32k3xx: lpspi dma invalidate cache after exchange
e71618d60e [BACKPORT] s32k3xx:lpi2c fix status handeling & race
6f59cc3659 [BACKPORT] s32k1xx:lpi2c fix status handeling & race
1e316d7e32 [BACKPORT] imxrt: flexcan use hpwork for receiving frames
67c1c59865 [BACKPORT] net/can can_readahead_timestamp always free iob
8be831a4ff [BACKPORT] imxrt: fix txdeadline add ecc/fd support
00a68b7668 [BACKPORT] fs/cromfs: Fix faulty DEBUGASSERT() check
d5cf545d6e [BACKPORT] S32K3XX EMAC MCAST support Fix compile warning when ioctl is not enabled
4265c830fa [BACKPORT] imxrt:edma {s|d}last needs to be total xfer size
24b4d44896 [BACKPORT] s32k3xx:edma {s|d}last needs to be total xfer size
eed0482f64 [BACKPORT] s32k1xx:edma {s|d}last needs to be total xfer size
36aab4146a [BACKPORT] kinetis:edma {s|d}last needs to be total xfer size
a0faf31f6f [BACKPORT] arch/stm32f7: fixes for pinmap
eb8255121d [BACKPORT] stm32h7:sdmmc It is not an error if no wait was needed
062044fe41 [BACKPORT] board nucleo-h743zi:Rework board.h not use CONFIG_STM32_USE_LEGACY_PINMAP
e03f9d3917 [BACKPORT] board olimexino-stm32:Rework board.h not use CONFIG_STM32_USE_LEGACY_PINMAP
4c3a467415 [BACKPORT] stm32l5:pinmap Add suffix to all pins and add legacy pinmap
153069ed40 [BACKPORT] stm32wb:pinmap Add suffix to all pins and add legacy pinmap
d84d737f89 [BACKPORT] stm32f0l0g0:stm32f0{3|5|7|9}x_pinmap & stm32g0_pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
5fc7071ac1 [BACKPORT] stm32l4:stm32l4x{3|4|5|6|r}xx_pinmap pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
20061c2aab [BACKPORT] stm32:stm32f10{0|2|3{c|r|v|z}|5{r|v}|7v}_pinmap refactor
4d1f83d484 [BACKPORT] stm32:stm32l15xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
2dfa3f2601 [BACKPORT] stm32:stm32g4xx{c|k|r|m|v|q} pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
d206327809 [BACKPORT] stm32:stm32f3{0|3|7}xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
95e66ab508 [BACKPORT] stm32:stm32f20xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
d2fd9178ad [BACKPORT] stm32:f4/f412 pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
a9df45166d [BACKPORT] stm32f7:pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
07dd2b424e [BACKPORT] stm32h7:pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
1e3065344f [BACKPORT] stm32u5:stm32u585xx_pinmap Fix typo
0a05365a90 [BACKPORT] stm32wl5:pinmap Fix typo
e3834138dc [BACKPORT] tools:Add STM32 Pin migration tool
df851a8768 [BACKPORT] stm32h7/rcc: make VOS0 configurable from board.h also for stm32h7x7xx
d75dfcf1e9 [BACKPORT] stm32h7/rcc: make VOS0 configurable from board.h
963f35f4fc [BACKPORT] {stm32,stm32f7,stm32h7,stm32l4,efm32}/otg: rasie an assertion if IN request is not possible to transfer
de2fcc6668 [BACKPORT] {stm32f7,stm32h7,stm32l4}/sdmmc: callback support requires HPWORK
6929144fc2 [BACKPORT] stm32h7/otgdev: FS transceiver must be enabled if OTGFS enabled
a2078afaea [BACKPORT] stm32h7/otg: add support for external ULPI
26e1246c86 [BACKPORT] stm32h7/rcc: OTGHS ULPI works only in VOS0
cd6daa185e [BACKPORT] stm32h7: update ULPI pins
c73c261ae3 [BACKPORT] arch/boards: fix stm32f411-mininum:nsh compilation failure after enabling IRQMONITOR
8078f134ef [BACKPORT] arch/stm32/stm32.h: do not include stm32_usbdev.h if not supported
60e884fa92 [BACKPORT] {stm32,stm32l4,stm32f0l0g0}/otg: move STM32_NENDPOINTS definitions to header files
dda297cb78 [BACKPORT] arch/arm/src/stm32/hardware: Fix register define
362b976b0e [BACKPORT] arch/arm/src/stm32/hardware: Add stm32g4 rcc apb1 timer enable compatibility
434fd71f2c [BACKPORT] {stm32/stm32l4/stm32f7/stm32h7/efm32}/otgdev: remove invalid use of the priv field for EP
2476d24e8c [BACKPORT] {stm32f7,stm32h7}/otg: fix compilation for USBDEV when USB_DEBUG=y
eb43c582ea [BACKPORT] drivers/mtd/ramtron: change nsectors size to uint32
20f61ff0d5 [BACKPORT] fs/littlefs: add full support for LittleFS block device cfg in Kconfig
60471fbf8c [BACKPORT] drivers/mtd: add Kconfig options for RAMTRON emulated page & sector size
- re-enable once the estimator selector respects configured mag
priority (at least initially) or is otherwise able to automatically
prefer an external mag over internal
- for SITL disabled because the full matrix of esitmator instances
(IMUs X mags) was too many topics for logger currently
This consolidates the version/revision detection function.
This should allow for actual changes in a follow up commit.
Signed-off-by: Julian Oes <julian@oes.ch>
Bootloader needs to have a mechanism to de-initialize crypto, in case some HW accelerator
is being used. This adds the needed function for it
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Eric Katzfey
Eric Katzfey
Peter van der Perk
David Sidrane
Peter van der Perk
Beat Küng
Niklas Hauser
robbie-sps
Ville Juven
Igor Mišić
Jukka Laitinen
Daniel Agar
Julian Oes