2018-01-05 02:19:51 -04:00
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/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Code by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#pragma once
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#include <AP_HAL/utility/RingBuffer.h>
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#include "AP_HAL_ChibiOS.h"
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#include "shared_dma.h"
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2018-03-06 18:41:03 -04:00
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#include "Semaphores.h"
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2018-01-05 02:19:51 -04:00
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#define RX_BOUNCE_BUFSIZE 128
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#define TX_BOUNCE_BUFSIZE 64
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2018-02-05 22:40:30 -04:00
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#define UART_MAX_DRIVERS 7
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2018-01-13 00:02:05 -04:00
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class ChibiOS::UARTDriver : public AP_HAL::UARTDriver {
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2018-01-05 02:19:51 -04:00
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public:
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UARTDriver(uint8_t serial_num);
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2018-01-05 02:19:51 -04:00
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void begin(uint32_t b);
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void begin(uint32_t b, uint16_t rxS, uint16_t txS);
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void end();
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void flush();
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bool is_initialized();
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void set_blocking_writes(bool blocking);
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bool tx_pending();
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uint32_t available() override;
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uint32_t txspace() override;
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int16_t read() override;
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2018-01-21 15:45:31 -04:00
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void _timer_tick(void) override;
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2018-01-05 02:19:51 -04:00
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size_t write(uint8_t c);
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size_t write(const uint8_t *buffer, size_t size);
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2018-04-02 03:00:36 -03:00
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// lock a port for exclusive use. Use a key of 0 to unlock
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bool lock_port(uint32_t key) override;
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// write to a locked port. If port is locked and key is not correct then 0 is returned
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// and write is discarded
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size_t write_locked(const uint8_t *buffer, size_t size, uint32_t key) override;
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2018-01-05 02:19:51 -04:00
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struct SerialDef {
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BaseSequentialStream* serial;
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bool is_usb;
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bool dma_rx;
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uint8_t dma_rx_stream_id;
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uint32_t dma_rx_channel_id;
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bool dma_tx;
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uint8_t dma_tx_stream_id;
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uint32_t dma_tx_channel_id;
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ioline_t rts_line;
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uint8_t get_index(void) const {
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return uint8_t(this - &_serial_tab[0]);
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}
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};
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bool wait_timeout(uint16_t n, uint32_t timeout_ms) override;
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2018-01-10 17:50:25 -04:00
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void set_flow_control(enum flow_control flow_control) override;
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enum flow_control get_flow_control(void) override { return _flow_control; }
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2018-01-21 16:28:29 -04:00
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// allow for low latency writes
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bool set_unbuffered_writes(bool on) override;
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2018-01-21 18:31:22 -04:00
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void configure_parity(uint8_t v) override;
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void set_stop_bits(int n) override;
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2018-05-15 21:42:31 -03:00
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/*
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return timestamp estimate in microseconds for when the start of
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a nbytes packet arrived on the uart. This should be treated as a
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time constraint, not an exact time. It is guaranteed that the
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packet did not start being received after this time, but it
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could have been in a system buffer before the returned time.
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This takes account of the baudrate of the link. For transports
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that have no baudrate (such as USB) the time estimate may be
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less accurate.
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A return value of zero means the HAL does not support this API
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*/
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2018-05-16 18:01:14 -03:00
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uint64_t receive_time_constraint_us(uint16_t nbytes) override;
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private:
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bool tx_bounce_buf_ready;
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const SerialDef &sdef;
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// thread used for all UARTs
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static thread_t *uart_thread_ctx;
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// last time we ran the uart thread
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static uint32_t last_thread_run_us;
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// table to find UARTDrivers from serial number, used for event handling
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static UARTDriver *uart_drivers[UART_MAX_DRIVERS];
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// index into uart_drivers table
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uint8_t serial_num;
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// key for a locked port
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uint32_t lock_key;
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2018-01-05 02:19:51 -04:00
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uint32_t _baudrate;
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uint16_t tx_len;
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2018-03-01 20:46:30 -04:00
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#if HAL_USE_SERIAL == TRUE
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SerialConfig sercfg;
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#endif
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const thread_t* _uart_owner_thd;
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struct {
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// thread waiting for data
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thread_t *thread_ctx;
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// number of bytes needed
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uint16_t n;
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} _wait;
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// we use in-task ring buffers to reduce the system call cost
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// of ::read() and ::write() in the main loop
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2018-05-31 22:18:37 -03:00
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uint8_t *rx_bounce_buf;
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uint8_t *tx_bounce_buf;
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ByteBuffer _readbuf{0};
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ByteBuffer _writebuf{0};
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Semaphore _write_mutex;
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const stm32_dma_stream_t* rxdma;
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const stm32_dma_stream_t* txdma;
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bool _in_timer;
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bool _blocking_writes;
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bool _initialised;
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bool _device_initialised;
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bool _lock_rx_in_timer_tick = false;
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Shared_DMA *dma_handle;
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static const SerialDef _serial_tab[];
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2018-05-15 21:42:31 -03:00
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// timestamp for receiving data on the UART, avoiding a lock
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uint64_t _receive_timestamp[2];
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uint8_t _receive_timestamp_idx;
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2018-01-10 17:50:25 -04:00
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// handling of flow control
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enum flow_control _flow_control = FLOW_CONTROL_DISABLE;
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bool _rts_is_active;
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uint32_t _last_write_completed_us;
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uint32_t _first_write_started_us;
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2018-03-14 05:51:04 -03:00
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2018-01-21 16:28:29 -04:00
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// set to true for unbuffered writes (low latency writes)
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bool unbuffered_writes;
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static void rx_irq_cb(void* sd);
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static void rxbuff_full_irq(void* self, uint32_t flags);
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static void tx_complete(void* self, uint32_t flags);
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2018-03-14 03:06:30 -03:00
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void dma_tx_allocate(Shared_DMA *ctx);
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void dma_tx_deallocate(Shared_DMA *ctx);
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void update_rts_line(void);
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2018-03-14 05:51:04 -03:00
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void check_dma_tx_completion(void);
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2018-01-21 16:28:29 -04:00
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void write_pending_bytes_DMA(uint32_t n);
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void write_pending_bytes_NODMA(uint32_t n);
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void write_pending_bytes(void);
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2018-02-05 22:40:30 -04:00
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2018-05-15 21:42:31 -03:00
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void receive_timestamp_update(void);
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2018-02-05 22:40:30 -04:00
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void thread_init();
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static void uart_thread(void *);
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};
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