2018-01-05 02:19:51 -04:00
|
|
|
/*
|
|
|
|
* This file is free software: you can redistribute it and/or modify it
|
|
|
|
* under the terms of the GNU General Public License as published by the
|
|
|
|
* Free Software Foundation, either version 3 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This file is distributed in the hope that it will be useful, but
|
|
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
|
|
|
* See the GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License along
|
|
|
|
* with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
#include "SPIDevice.h"
|
|
|
|
|
|
|
|
#include <AP_HAL/AP_HAL.h>
|
2018-12-27 21:05:06 -04:00
|
|
|
#include <AP_Math/AP_Math.h>
|
2018-01-05 02:19:51 -04:00
|
|
|
#include <AP_HAL/utility/OwnPtr.h>
|
2019-04-28 05:13:09 -03:00
|
|
|
#include <AP_InternalError/AP_InternalError.h>
|
2018-01-09 17:18:28 -04:00
|
|
|
#include "Util.h"
|
2018-01-05 02:19:51 -04:00
|
|
|
#include "Scheduler.h"
|
|
|
|
#include "Semaphores.h"
|
|
|
|
#include <stdio.h>
|
2018-05-30 01:22:49 -03:00
|
|
|
#include "hwdef/common/stm32_util.h"
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-03-01 20:46:30 -04:00
|
|
|
#if HAL_USE_SPI == TRUE
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
using namespace ChibiOS;
|
2018-01-09 17:18:28 -04:00
|
|
|
extern const AP_HAL::HAL& hal;
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-01-05 04:36:56 -04:00
|
|
|
// SPI mode numbers
|
2019-02-06 17:09:07 -04:00
|
|
|
#if defined(STM32H7)
|
|
|
|
#define SPIDEV_MODE0 0
|
|
|
|
#define SPIDEV_MODE1 SPI_CFG2_CPHA
|
|
|
|
#define SPIDEV_MODE2 SPI_CFG2_CPOL
|
|
|
|
#define SPIDEV_MODE3 SPI_CFG2_CPOL | SPI_CFG2_CPHA
|
2019-02-10 17:39:31 -04:00
|
|
|
|
|
|
|
#define SPI1_CLOCK STM32_SPI1CLK
|
|
|
|
#define SPI2_CLOCK STM32_SPI2CLK
|
|
|
|
#define SPI3_CLOCK STM32_SPI3CLK
|
|
|
|
#define SPI4_CLOCK STM32_SPI4CLK
|
|
|
|
#define SPI5_CLOCK STM32_SPI5CLK
|
|
|
|
#define SPI6_CLOCK STM32_SPI6CLK
|
|
|
|
|
|
|
|
#else // F4 and F7
|
2018-01-05 04:36:56 -04:00
|
|
|
#define SPIDEV_MODE0 0
|
|
|
|
#define SPIDEV_MODE1 SPI_CR1_CPHA
|
|
|
|
#define SPIDEV_MODE2 SPI_CR1_CPOL
|
|
|
|
#define SPIDEV_MODE3 SPI_CR1_CPOL | SPI_CR1_CPHA
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
#define SPI1_CLOCK STM32_PCLK2
|
|
|
|
#define SPI2_CLOCK STM32_PCLK1
|
|
|
|
#define SPI3_CLOCK STM32_PCLK1
|
|
|
|
#define SPI4_CLOCK STM32_PCLK2
|
2018-05-29 08:01:58 -03:00
|
|
|
#define SPI5_CLOCK STM32_PCLK2
|
|
|
|
#define SPI6_CLOCK STM32_PCLK2
|
2019-02-10 17:39:31 -04:00
|
|
|
#endif
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-03-07 17:42:35 -04:00
|
|
|
// expected bus clock speeds
|
2018-05-29 08:01:58 -03:00
|
|
|
static const uint32_t bus_clocks[6] = {
|
|
|
|
SPI1_CLOCK, SPI2_CLOCK, SPI3_CLOCK, SPI4_CLOCK, SPI5_CLOCK, SPI6_CLOCK
|
2018-03-07 17:42:35 -04:00
|
|
|
};
|
|
|
|
|
2019-10-20 10:31:12 -03:00
|
|
|
static const struct SPIDriverInfo {
|
2018-01-05 02:19:51 -04:00
|
|
|
SPIDriver *driver;
|
2018-01-05 04:36:56 -04:00
|
|
|
uint8_t busid; // used for device IDs in parameters
|
2018-01-05 02:19:51 -04:00
|
|
|
uint8_t dma_channel_rx;
|
|
|
|
uint8_t dma_channel_tx;
|
2018-01-11 21:01:06 -04:00
|
|
|
} spi_devices[] = { HAL_SPI_BUS_LIST };
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-01-11 21:01:06 -04:00
|
|
|
// device list comes from hwdef.dat
|
2018-03-01 20:46:30 -04:00
|
|
|
ChibiOS::SPIDesc SPIDeviceManager::device_table[] = { HAL_SPI_DEVICE_LIST };
|
2018-01-05 02:19:51 -04:00
|
|
|
|
|
|
|
SPIBus::SPIBus(uint8_t _bus) :
|
|
|
|
DeviceBus(APM_SPI_PRIORITY),
|
|
|
|
bus(_bus)
|
|
|
|
{
|
2018-06-04 08:27:54 -03:00
|
|
|
chMtxObjectInit(&dma_lock);
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
// allow for sharing of DMA channels with other peripherals
|
|
|
|
dma_handle = new Shared_DMA(spi_devices[bus].dma_channel_rx,
|
|
|
|
spi_devices[bus].dma_channel_tx,
|
2018-03-14 03:06:30 -03:00
|
|
|
FUNCTOR_BIND_MEMBER(&SPIBus::dma_allocate, void, Shared_DMA *),
|
|
|
|
FUNCTOR_BIND_MEMBER(&SPIBus::dma_deallocate, void, Shared_DMA *));
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
allocate DMA channel
|
|
|
|
*/
|
2018-03-14 03:06:30 -03:00
|
|
|
void SPIBus::dma_allocate(Shared_DMA *ctx)
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
|
|
|
// nothing to do as we call spiStart() on each transaction
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
deallocate DMA channel
|
|
|
|
*/
|
2018-03-14 03:06:30 -03:00
|
|
|
void SPIBus::dma_deallocate(Shared_DMA *ctx)
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2019-10-20 10:31:12 -03:00
|
|
|
chMtxLock(&dma_lock);
|
2018-01-05 02:19:51 -04:00
|
|
|
// another non-SPI peripheral wants one of our DMA channels
|
2018-02-02 23:26:13 -04:00
|
|
|
if (spi_started) {
|
|
|
|
spiStop(spi_devices[bus].driver);
|
|
|
|
spi_started = false;
|
|
|
|
}
|
2019-10-20 10:31:12 -03:00
|
|
|
chMtxUnlock(&dma_lock);
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
SPIDevice::SPIDevice(SPIBus &_bus, SPIDesc &_device_desc)
|
|
|
|
: bus(_bus)
|
|
|
|
, device_desc(_device_desc)
|
|
|
|
{
|
2018-01-05 04:36:56 -04:00
|
|
|
set_device_bus(spi_devices[_bus.bus].busid);
|
2018-01-05 02:19:51 -04:00
|
|
|
set_device_address(_device_desc.device);
|
|
|
|
freq_flag_low = derive_freq_flag(device_desc.lowspeed);
|
|
|
|
freq_flag_high = derive_freq_flag(device_desc.highspeed);
|
|
|
|
|
|
|
|
set_speed(AP_HAL::Device::SPEED_LOW);
|
|
|
|
|
|
|
|
asprintf(&pname, "SPI:%s:%u:%u",
|
|
|
|
device_desc.name,
|
|
|
|
(unsigned)bus.bus, (unsigned)device_desc.device);
|
2020-07-30 11:05:25 -03:00
|
|
|
AP_HAL::SPIDevice::setup_bankselect_callback(device_desc.bank_select_cb);
|
2018-01-05 02:19:51 -04:00
|
|
|
//printf("SPI device %s on %u:%u at speed %u mode %u\n",
|
|
|
|
// device_desc.name,
|
|
|
|
// (unsigned)bus.bus, (unsigned)device_desc.device,
|
|
|
|
// (unsigned)frequency, (unsigned)device_desc.mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
SPIDevice::~SPIDevice()
|
|
|
|
{
|
|
|
|
//printf("SPI device %s on %u:%u closed\n", device_desc.name,
|
|
|
|
// (unsigned)bus.bus, (unsigned)device_desc.device);
|
|
|
|
free(pname);
|
|
|
|
}
|
|
|
|
|
2018-04-28 21:09:09 -03:00
|
|
|
SPIDriver * SPIDevice::get_driver() {
|
|
|
|
return spi_devices[device_desc.bus].driver;
|
|
|
|
}
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
bool SPIDevice::set_speed(AP_HAL::Device::Speed speed)
|
|
|
|
{
|
|
|
|
switch (speed) {
|
|
|
|
case AP_HAL::Device::SPEED_HIGH:
|
|
|
|
freq_flag = freq_flag_high;
|
|
|
|
break;
|
|
|
|
case AP_HAL::Device::SPEED_LOW:
|
|
|
|
freq_flag = freq_flag_low;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-12-27 21:05:06 -04:00
|
|
|
/*
|
|
|
|
setup a bus slowdown factor for high speed mode
|
|
|
|
*/
|
|
|
|
void SPIDevice::set_slowdown(uint8_t slowdown)
|
|
|
|
{
|
|
|
|
slowdown = constrain_int16(slowdown+1, 1, 32);
|
|
|
|
freq_flag_high = derive_freq_flag(device_desc.highspeed / slowdown);
|
|
|
|
}
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
/*
|
|
|
|
low level transfer function
|
|
|
|
*/
|
2019-04-28 05:13:09 -03:00
|
|
|
bool SPIDevice::do_transfer(const uint8_t *send, uint8_t *recv, uint32_t len)
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
|
|
|
bool old_cs_forced = cs_forced;
|
|
|
|
|
|
|
|
if (!set_chip_select(true)) {
|
2019-04-28 05:13:09 -03:00
|
|
|
return false;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
2018-01-09 17:18:28 -04:00
|
|
|
|
2019-04-28 05:13:09 -03:00
|
|
|
bool ret = true;
|
2018-01-09 17:18:28 -04:00
|
|
|
|
2019-02-18 18:39:16 -04:00
|
|
|
#if defined(HAL_SPI_USE_POLLED)
|
2021-06-10 06:13:34 -03:00
|
|
|
for (uint32_t i=0; i<len; i++) {
|
2021-09-27 02:49:45 -03:00
|
|
|
const uint8_t b = spiPolledExchange(spi_devices[device_desc.bus].driver, send?send[i]:0);
|
2019-02-18 18:39:16 -04:00
|
|
|
if (recv) {
|
2021-09-27 02:49:45 -03:00
|
|
|
recv[i] = b;
|
2019-02-18 18:39:16 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
2020-01-17 00:22:44 -04:00
|
|
|
if (!bus.bouncebuffer_setup(send, len, recv, len)) {
|
|
|
|
set_chip_select(old_cs_forced);
|
|
|
|
return false;
|
|
|
|
}
|
2019-04-28 05:13:09 -03:00
|
|
|
osalSysLock();
|
2019-05-16 04:57:35 -03:00
|
|
|
hal.util->persistent_data.spi_count++;
|
2019-03-10 00:01:37 -04:00
|
|
|
if (send == nullptr) {
|
2019-04-28 05:13:09 -03:00
|
|
|
spiStartReceiveI(spi_devices[device_desc.bus].driver, len, recv);
|
2019-03-10 00:01:37 -04:00
|
|
|
} else if (recv == nullptr) {
|
2019-04-28 05:13:09 -03:00
|
|
|
spiStartSendI(spi_devices[device_desc.bus].driver, len, send);
|
2019-03-10 00:01:37 -04:00
|
|
|
} else {
|
2019-04-28 05:13:09 -03:00
|
|
|
spiStartExchangeI(spi_devices[device_desc.bus].driver, len, send, recv);
|
|
|
|
}
|
|
|
|
// we allow SPI transfers to take a maximum of 20ms plus 32us per
|
|
|
|
// byte. This covers all use cases in ArduPilot. We don't ever
|
|
|
|
// expect this timeout to trigger unless there is a severe MCU
|
|
|
|
// error
|
|
|
|
const uint32_t timeout_us = 20000U + len * 32U;
|
2019-11-01 07:15:34 -03:00
|
|
|
msg_t msg = osalThreadSuspendTimeoutS(&spi_devices[device_desc.bus].driver->thread, TIME_US2I(timeout_us));
|
2019-04-28 05:13:09 -03:00
|
|
|
osalSysUnlock();
|
|
|
|
if (msg == MSG_TIMEOUT) {
|
|
|
|
ret = false;
|
2020-03-10 22:21:04 -03:00
|
|
|
if (!hal.scheduler->in_expected_delay()) {
|
2020-04-29 21:40:45 -03:00
|
|
|
INTERNAL_ERROR(AP_InternalError::error_t::spi_fail);
|
2020-03-10 22:21:04 -03:00
|
|
|
}
|
2019-04-28 05:13:09 -03:00
|
|
|
spiAbort(spi_devices[device_desc.bus].driver);
|
2019-03-10 00:01:37 -04:00
|
|
|
}
|
2018-06-02 00:27:02 -03:00
|
|
|
bus.bouncebuffer_finish(send, recv, len);
|
2019-02-18 18:39:16 -04:00
|
|
|
#endif
|
2018-01-05 02:19:51 -04:00
|
|
|
set_chip_select(old_cs_forced);
|
2019-04-28 05:13:09 -03:00
|
|
|
return ret;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2021-09-27 04:39:40 -03:00
|
|
|
/*
|
|
|
|
this pulses the clock for n bytes. The data is ignored.
|
|
|
|
*/
|
2018-05-26 05:59:41 -03:00
|
|
|
bool SPIDevice::clock_pulse(uint32_t n)
|
|
|
|
{
|
2021-09-27 04:39:40 -03:00
|
|
|
msg_t msg;
|
|
|
|
const uint32_t timeout_us = 20000U + n * 32U;
|
2018-05-26 05:59:41 -03:00
|
|
|
if (!cs_forced) {
|
|
|
|
//special mode to init sdcard without cs asserted
|
2020-01-18 17:42:33 -04:00
|
|
|
bus.semaphore.take_blocking();
|
2018-05-26 05:59:41 -03:00
|
|
|
acquire_bus(true, true);
|
2021-09-27 04:39:40 -03:00
|
|
|
osalSysLock();
|
|
|
|
spiStartIgnoreI(spi_devices[device_desc.bus].driver, n);
|
|
|
|
msg = osalThreadSuspendTimeoutS(&spi_devices[device_desc.bus].driver->thread, TIME_US2I(timeout_us));
|
|
|
|
osalSysUnlock();
|
|
|
|
if (msg == MSG_TIMEOUT) {
|
|
|
|
spiAbort(spi_devices[device_desc.bus].driver);
|
|
|
|
}
|
2018-05-26 05:59:41 -03:00
|
|
|
acquire_bus(false, true);
|
|
|
|
bus.semaphore.give();
|
|
|
|
} else {
|
2021-04-15 05:04:58 -03:00
|
|
|
if (!bus.semaphore.check_owner()) {
|
|
|
|
return false;
|
|
|
|
}
|
2021-09-27 04:39:40 -03:00
|
|
|
osalSysLock();
|
|
|
|
spiStartIgnoreI(spi_devices[device_desc.bus].driver, n);
|
|
|
|
msg = osalThreadSuspendTimeoutS(&spi_devices[device_desc.bus].driver->thread, TIME_US2I(timeout_us));
|
|
|
|
osalSysUnlock();
|
|
|
|
if (msg == MSG_TIMEOUT) {
|
|
|
|
spiAbort(spi_devices[device_desc.bus].driver);
|
|
|
|
}
|
2018-05-26 05:59:41 -03:00
|
|
|
}
|
2021-09-27 04:39:40 -03:00
|
|
|
return msg != MSG_TIMEOUT;
|
2018-05-26 05:59:41 -03:00
|
|
|
}
|
|
|
|
|
2019-02-06 17:09:07 -04:00
|
|
|
uint32_t SPIDevice::derive_freq_flag_bus(uint8_t busid, uint32_t _frequency)
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2018-03-07 17:42:35 -04:00
|
|
|
uint32_t spi_clock_freq = SPI1_CLOCK;
|
2018-08-02 20:27:17 -03:00
|
|
|
if (busid > 0 && uint8_t(busid-1) < ARRAY_SIZE(bus_clocks)) {
|
2018-04-17 19:05:08 -03:00
|
|
|
spi_clock_freq = bus_clocks[busid-1] / 2;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2018-03-07 17:42:35 -04:00
|
|
|
// find first divisor that brings us below the desired SPI clock
|
|
|
|
uint32_t i = 0;
|
|
|
|
while (spi_clock_freq > _frequency && i<7) {
|
|
|
|
spi_clock_freq >>= 1;
|
|
|
|
i++;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2018-03-07 17:42:35 -04:00
|
|
|
// assuming the bitrate bits are consecutive in the CR1 register,
|
|
|
|
// we can just multiply by BR_0 to get the right bits for the desired
|
|
|
|
// scaling
|
2019-02-06 17:09:07 -04:00
|
|
|
#if defined(STM32H7)
|
|
|
|
return (i * SPI_CFG1_MBR_0) | SPI_CFG1_DSIZE_VALUE(7); // 8 bit transfers
|
|
|
|
#else
|
2018-03-07 17:42:35 -04:00
|
|
|
return i * SPI_CR1_BR_0;
|
2019-02-06 17:09:07 -04:00
|
|
|
#endif
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2019-02-06 17:09:07 -04:00
|
|
|
uint32_t SPIDevice::derive_freq_flag(uint32_t _frequency)
|
2018-05-29 08:01:58 -03:00
|
|
|
{
|
|
|
|
uint8_t busid = spi_devices[device_desc.bus].busid;
|
|
|
|
return derive_freq_flag_bus(busid, _frequency);
|
|
|
|
}
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
bool SPIDevice::transfer(const uint8_t *send, uint32_t send_len,
|
|
|
|
uint8_t *recv, uint32_t recv_len)
|
|
|
|
{
|
2018-02-08 18:54:31 -04:00
|
|
|
if (!bus.semaphore.check_owner()) {
|
|
|
|
return false;
|
|
|
|
}
|
2018-05-26 05:59:41 -03:00
|
|
|
if ((send_len == recv_len && send == recv) || !send || !recv) {
|
2018-01-05 02:19:51 -04:00
|
|
|
// simplest cases, needed for DMA
|
2019-04-28 05:13:09 -03:00
|
|
|
return do_transfer(send, recv, recv_len?recv_len:send_len);
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
2018-01-09 17:18:28 -04:00
|
|
|
uint8_t buf[send_len+recv_len];
|
2018-01-05 02:19:51 -04:00
|
|
|
if (send_len > 0) {
|
|
|
|
memcpy(buf, send, send_len);
|
|
|
|
}
|
|
|
|
if (recv_len > 0) {
|
|
|
|
memset(&buf[send_len], 0, recv_len);
|
|
|
|
}
|
2019-04-28 05:13:09 -03:00
|
|
|
bool ret = do_transfer(buf, buf, send_len+recv_len);
|
|
|
|
if (ret && recv_len > 0) {
|
2018-01-05 02:19:51 -04:00
|
|
|
memcpy(recv, &buf[send_len], recv_len);
|
|
|
|
}
|
2019-04-28 05:13:09 -03:00
|
|
|
return ret;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
bool SPIDevice::transfer_fullduplex(const uint8_t *send, uint8_t *recv, uint32_t len)
|
|
|
|
{
|
2021-04-15 05:04:58 -03:00
|
|
|
if (!bus.semaphore.check_owner()) {
|
|
|
|
return false;
|
|
|
|
}
|
2018-01-05 02:19:51 -04:00
|
|
|
uint8_t buf[len];
|
|
|
|
memcpy(buf, send, len);
|
2019-04-28 05:13:09 -03:00
|
|
|
bool ret = do_transfer(buf, buf, len);
|
|
|
|
if (ret) {
|
|
|
|
memcpy(recv, buf, len);
|
|
|
|
}
|
|
|
|
return ret;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
AP_HAL::Semaphore *SPIDevice::get_semaphore()
|
|
|
|
{
|
|
|
|
return &bus.semaphore;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
AP_HAL::Device::PeriodicHandle SPIDevice::register_periodic_callback(uint32_t period_usec, AP_HAL::Device::PeriodicCb cb)
|
|
|
|
{
|
|
|
|
return bus.register_periodic_callback(period_usec, cb, this);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool SPIDevice::adjust_periodic_callback(AP_HAL::Device::PeriodicHandle h, uint32_t period_usec)
|
|
|
|
{
|
|
|
|
return bus.adjust_timer(h, period_usec);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2018-04-28 21:09:09 -03:00
|
|
|
used to acquire bus and (optionally) assert cs
|
|
|
|
*/
|
|
|
|
bool SPIDevice::acquire_bus(bool set, bool skip_cs)
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2021-04-15 05:04:58 -03:00
|
|
|
if (!bus.semaphore.check_owner()) {
|
|
|
|
return false;
|
|
|
|
}
|
2018-01-05 02:19:51 -04:00
|
|
|
if (set && cs_forced) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
if (!set && !cs_forced) {
|
2018-05-21 18:51:05 -03:00
|
|
|
return false;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
if (!set && cs_forced) {
|
2018-04-28 21:09:09 -03:00
|
|
|
if(!skip_cs) {
|
|
|
|
spiUnselectI(spi_devices[device_desc.bus].driver); /* Slave Select de-assertion. */
|
|
|
|
}
|
2018-01-05 02:19:51 -04:00
|
|
|
spiReleaseBus(spi_devices[device_desc.bus].driver); /* Ownership release. */
|
|
|
|
cs_forced = false;
|
|
|
|
bus.dma_handle->unlock();
|
|
|
|
} else {
|
|
|
|
bus.dma_handle->lock();
|
|
|
|
spiAcquireBus(spi_devices[device_desc.bus].driver); /* Acquire ownership of the bus. */
|
|
|
|
bus.spicfg.end_cb = nullptr;
|
2018-01-11 21:01:06 -04:00
|
|
|
bus.spicfg.ssport = PAL_PORT(device_desc.pal_line);
|
|
|
|
bus.spicfg.sspad = PAL_PAD(device_desc.pal_line);
|
2019-02-06 17:09:07 -04:00
|
|
|
#if defined(STM32H7)
|
|
|
|
bus.spicfg.cfg1 = freq_flag;
|
|
|
|
bus.spicfg.cfg2 = device_desc.mode;
|
2019-03-10 06:32:32 -03:00
|
|
|
if (bus.spicfg.dummytx == nullptr) {
|
|
|
|
bus.spicfg.dummytx = (uint32_t *)malloc_dma(4);
|
|
|
|
memset(bus.spicfg.dummytx, 0xFF, 4);
|
|
|
|
}
|
|
|
|
if (bus.spicfg.dummyrx == nullptr) {
|
|
|
|
bus.spicfg.dummyrx = (uint32_t *)malloc_dma(4);
|
|
|
|
}
|
2019-02-06 17:09:07 -04:00
|
|
|
#else
|
2018-01-05 02:19:51 -04:00
|
|
|
bus.spicfg.cr1 = (uint16_t)(freq_flag | device_desc.mode);
|
|
|
|
bus.spicfg.cr2 = 0;
|
2019-02-06 17:09:07 -04:00
|
|
|
#endif
|
2018-02-03 15:59:43 -04:00
|
|
|
if (bus.spi_started) {
|
|
|
|
spiStop(spi_devices[device_desc.bus].driver);
|
|
|
|
bus.spi_started = false;
|
|
|
|
}
|
2018-01-05 02:19:51 -04:00
|
|
|
spiStart(spi_devices[device_desc.bus].driver, &bus.spicfg); /* Setup transfer parameters. */
|
2018-02-02 23:26:13 -04:00
|
|
|
bus.spi_started = true;
|
2018-04-28 21:09:09 -03:00
|
|
|
if(!skip_cs) {
|
|
|
|
spiSelectI(spi_devices[device_desc.bus].driver); /* Slave Select assertion. */
|
|
|
|
}
|
2018-01-05 02:19:51 -04:00
|
|
|
cs_forced = true;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-04-28 21:09:09 -03:00
|
|
|
/*
|
|
|
|
allow for control of SPI chip select pin
|
|
|
|
*/
|
|
|
|
bool SPIDevice::set_chip_select(bool set) {
|
|
|
|
return acquire_bus(set, false);
|
|
|
|
}
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
/*
|
|
|
|
return a SPIDevice given a string device name
|
|
|
|
*/
|
|
|
|
AP_HAL::OwnPtr<AP_HAL::SPIDevice>
|
|
|
|
SPIDeviceManager::get_device(const char *name)
|
|
|
|
{
|
|
|
|
/* Find the bus description in the table */
|
|
|
|
uint8_t i;
|
2018-08-02 20:27:17 -03:00
|
|
|
for (i = 0; i<ARRAY_SIZE(device_table); i++) {
|
2018-01-05 02:19:51 -04:00
|
|
|
if (strcmp(device_table[i].name, name) == 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2018-08-02 20:27:17 -03:00
|
|
|
if (i == ARRAY_SIZE(device_table)) {
|
2018-01-05 02:19:51 -04:00
|
|
|
return AP_HAL::OwnPtr<AP_HAL::SPIDevice>(nullptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
SPIDesc &desc = device_table[i];
|
|
|
|
|
|
|
|
// find the bus
|
|
|
|
SPIBus *busp;
|
|
|
|
for (busp = buses; busp; busp = (SPIBus *)busp->next) {
|
|
|
|
if (busp->bus == desc.bus) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (busp == nullptr) {
|
|
|
|
// create a new one
|
|
|
|
busp = new SPIBus(desc.bus);
|
|
|
|
if (busp == nullptr) {
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
busp->next = buses;
|
|
|
|
busp->bus = desc.bus;
|
|
|
|
|
|
|
|
buses = busp;
|
|
|
|
}
|
|
|
|
|
|
|
|
return AP_HAL::OwnPtr<AP_HAL::SPIDevice>(new SPIDevice(*busp, desc));
|
|
|
|
}
|
2018-03-01 20:46:30 -04:00
|
|
|
|
2018-03-07 17:42:35 -04:00
|
|
|
#ifdef HAL_SPI_CHECK_CLOCK_FREQ
|
2019-02-09 17:53:22 -04:00
|
|
|
|
2018-03-07 17:42:35 -04:00
|
|
|
/*
|
|
|
|
test clock frequencies. This measures the actual SPI clock
|
|
|
|
frequencies on all configured SPI buses. Used during board bringup
|
|
|
|
to validate clock configuration
|
|
|
|
*/
|
|
|
|
void SPIDevice::test_clock_freq(void)
|
|
|
|
{
|
|
|
|
// delay for USB to come up
|
|
|
|
hal.console->printf("Waiting for USB\n");
|
2019-02-09 17:53:22 -04:00
|
|
|
for (uint8_t i=0; i<3; i++) {
|
|
|
|
hal.scheduler->delay(1000);
|
2019-12-12 05:36:58 -04:00
|
|
|
hal.console->printf("Waiting %u\n", (unsigned)AP_HAL::millis());
|
2019-02-09 17:53:22 -04:00
|
|
|
}
|
2019-03-06 19:44:41 -04:00
|
|
|
hal.console->printf("CLOCKS=\n");
|
|
|
|
for (uint8_t i=0; i<ARRAY_SIZE(bus_clocks); i++) {
|
2019-12-12 05:36:58 -04:00
|
|
|
hal.console->printf("%u:%u ", unsigned(i+1), unsigned(bus_clocks[i]));
|
2019-03-06 19:44:41 -04:00
|
|
|
}
|
|
|
|
hal.console->printf("\n");
|
2018-03-07 17:42:35 -04:00
|
|
|
|
|
|
|
// we will send 1024 bytes without any CS asserted and measure the
|
|
|
|
// time it takes to do the transfer
|
|
|
|
uint16_t len = 1024;
|
2019-02-09 17:53:22 -04:00
|
|
|
uint8_t *buf1 = (uint8_t *)hal.util->malloc_type(len, AP_HAL::Util::MEM_DMA_SAFE);
|
|
|
|
uint8_t *buf2 = (uint8_t *)hal.util->malloc_type(len, AP_HAL::Util::MEM_DMA_SAFE);
|
2018-08-02 20:27:17 -03:00
|
|
|
for (uint8_t i=0; i<ARRAY_SIZE(spi_devices); i++) {
|
2018-03-07 17:42:35 -04:00
|
|
|
SPIConfig spicfg {};
|
2018-05-29 08:01:58 -03:00
|
|
|
const uint32_t target_freq = 2000000UL;
|
2018-03-07 17:42:35 -04:00
|
|
|
// use a clock divisor of 256 for maximum resolution
|
2019-02-06 17:09:07 -04:00
|
|
|
#if defined(STM32H7)
|
|
|
|
spicfg.cfg1 = derive_freq_flag_bus(spi_devices[i].busid, target_freq);
|
|
|
|
#else
|
2018-05-29 08:01:58 -03:00
|
|
|
spicfg.cr1 = derive_freq_flag_bus(spi_devices[i].busid, target_freq);
|
2019-02-06 17:09:07 -04:00
|
|
|
#endif
|
2018-03-07 17:42:35 -04:00
|
|
|
spiAcquireBus(spi_devices[i].driver);
|
|
|
|
spiStart(spi_devices[i].driver, &spicfg);
|
|
|
|
uint32_t t0 = AP_HAL::micros();
|
2019-02-09 17:53:22 -04:00
|
|
|
spiStartExchange(spi_devices[i].driver, len, buf1, buf2);
|
|
|
|
chSysLock();
|
|
|
|
msg_t msg = osalThreadSuspendTimeoutS(&spi_devices[i].driver->thread, TIME_MS2I(100));
|
|
|
|
chSysUnlock();
|
|
|
|
if (msg == MSG_TIMEOUT) {
|
|
|
|
spiAbort(spi_devices[i].driver);
|
|
|
|
hal.console->printf("SPI[%u] FAIL %p %p\n", spi_devices[i].busid, buf1, buf2);
|
|
|
|
spiStop(spi_devices[i].driver);
|
|
|
|
spiReleaseBus(spi_devices[i].driver);
|
|
|
|
continue;
|
|
|
|
}
|
2018-03-07 17:42:35 -04:00
|
|
|
uint32_t t1 = AP_HAL::micros();
|
|
|
|
spiStop(spi_devices[i].driver);
|
|
|
|
spiReleaseBus(spi_devices[i].driver);
|
2019-12-12 05:36:58 -04:00
|
|
|
hal.console->printf("SPI[%u] clock=%u\n", unsigned(spi_devices[i].busid), unsigned(1000000ULL * len * 8ULL / uint64_t(t1 - t0)));
|
2018-03-07 17:42:35 -04:00
|
|
|
}
|
2019-02-09 17:53:22 -04:00
|
|
|
hal.util->free_type(buf1, len, AP_HAL::Util::MEM_DMA_SAFE);
|
|
|
|
hal.util->free_type(buf2, len, AP_HAL::Util::MEM_DMA_SAFE);
|
2018-03-07 17:42:35 -04:00
|
|
|
}
|
|
|
|
#endif // HAL_SPI_CHECK_CLOCK_FREQ
|
|
|
|
|
|
|
|
#endif // HAL_USE_SPI
|