forked from rrcarlosr/Jetpack
956 lines
28 KiB
Plaintext
956 lines
28 KiB
Plaintext
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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/ {
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mods-simple-bus {
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compatible = "simple-bus";
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device_type = "mods-simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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mods-clocks {
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compatible = "nvidia,mods-clocks";
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status = "disabled";
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clocks = <&bpmp_clks TEGRA194_CLK_ACTMON>,
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<&bpmp_clks TEGRA194_CLK_ADSP>,
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<&bpmp_clks TEGRA194_CLK_ADSPNEON>,
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<&bpmp_clks TEGRA194_CLK_AHUB>,
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<&bpmp_clks TEGRA194_CLK_APB2APE>,
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<&bpmp_clks TEGRA194_CLK_APE>,
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<&bpmp_clks TEGRA194_CLK_AUD_MCLK>,
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<&bpmp_clks TEGRA194_CLK_AXI_CBB>,
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<&bpmp_clks TEGRA194_CLK_CAN1>,
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<&bpmp_clks TEGRA194_CLK_CAN1_HOST>,
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<&bpmp_clks TEGRA194_CLK_CAN2>,
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<&bpmp_clks TEGRA194_CLK_CAN2_HOST>,
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<&bpmp_clks TEGRA194_CLK_CEC>,
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<&bpmp_clks TEGRA194_CLK_CLK_M>,
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<&bpmp_clks TEGRA194_CLK_DMIC1>,
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<&bpmp_clks TEGRA194_CLK_DMIC2>,
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<&bpmp_clks TEGRA194_CLK_DMIC3>,
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<&bpmp_clks TEGRA194_CLK_DMIC4>,
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<&bpmp_clks TEGRA194_CLK_DPAUX>,
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<&bpmp_clks TEGRA194_CLK_DPAUX1>,
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<&bpmp_clks TEGRA194_CLK_ACLK>,
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<&bpmp_clks TEGRA194_CLK_MSS_ENCRYPT>,
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<&bpmp_clks TEGRA194_CLK_EQOS_RX_INPUT>,
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<&bpmp_clks TEGRA194_CLK_IQC2>,
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<&bpmp_clks TEGRA194_CLK_AON_APB>,
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<&bpmp_clks TEGRA194_CLK_AON_NIC>,
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<&bpmp_clks TEGRA194_CLK_AON_CPU_NIC>,
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<&bpmp_clks TEGRA194_CLK_PLLA1>,
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<&bpmp_clks TEGRA194_CLK_DSPK1>,
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<&bpmp_clks TEGRA194_CLK_DSPK2>,
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<&bpmp_clks TEGRA194_CLK_EMC>,
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<&bpmp_clks TEGRA194_CLK_EQOS_AXI>,
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<&bpmp_clks TEGRA194_CLK_EQOS_PTP_REF>,
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<&bpmp_clks TEGRA194_CLK_EQOS_RX>,
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<&bpmp_clks TEGRA194_CLK_EQOS_TX>,
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<&bpmp_clks TEGRA194_CLK_EXTPERIPH1>,
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<&bpmp_clks TEGRA194_CLK_EXTPERIPH2>,
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<&bpmp_clks TEGRA194_CLK_EXTPERIPH3>,
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<&bpmp_clks TEGRA194_CLK_EXTPERIPH4>,
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<&bpmp_clks TEGRA194_CLK_FUSE>,
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<&bpmp_clks TEGRA194_CLK_GPCCLK>,
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<&bpmp_clks TEGRA194_CLK_GPU_PWR>,
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<&bpmp_clks TEGRA194_CLK_HDA>,
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<&bpmp_clks TEGRA194_CLK_HDA2CODEC_2X>,
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<&bpmp_clks TEGRA194_CLK_HDA2HDMICODEC>,
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<&bpmp_clks TEGRA194_CLK_HOST1X>,
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<&bpmp_clks TEGRA194_CLK_HSIC_TRK>,
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<&bpmp_clks TEGRA194_CLK_I2C1>,
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<&bpmp_clks TEGRA194_CLK_I2C2>,
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<&bpmp_clks TEGRA194_CLK_I2C3>,
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<&bpmp_clks TEGRA194_CLK_I2C4>,
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<&bpmp_clks TEGRA194_CLK_I2C6>,
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<&bpmp_clks TEGRA194_CLK_I2C7>,
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<&bpmp_clks TEGRA194_CLK_I2C8>,
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<&bpmp_clks TEGRA194_CLK_I2C9>,
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<&bpmp_clks TEGRA194_CLK_I2S1>,
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<&bpmp_clks TEGRA194_CLK_I2S1_SYNC_INPUT>,
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<&bpmp_clks TEGRA194_CLK_I2S2>,
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<&bpmp_clks TEGRA194_CLK_I2S2_SYNC_INPUT>,
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<&bpmp_clks TEGRA194_CLK_I2S3>,
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<&bpmp_clks TEGRA194_CLK_I2S3_SYNC_INPUT>,
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<&bpmp_clks TEGRA194_CLK_I2S4>,
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<&bpmp_clks TEGRA194_CLK_I2S4_SYNC_INPUT>,
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<&bpmp_clks TEGRA194_CLK_I2S5>,
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<&bpmp_clks TEGRA194_CLK_I2S5_SYNC_INPUT>,
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<&bpmp_clks TEGRA194_CLK_I2S6>,
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<&bpmp_clks TEGRA194_CLK_I2S6_SYNC_INPUT>,
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<&bpmp_clks TEGRA194_CLK_IQC1>,
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<&bpmp_clks TEGRA194_CLK_ISP>,
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<&bpmp_clks TEGRA194_CLK_KFUSE>,
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<&bpmp_clks TEGRA194_CLK_MAUD>,
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<&bpmp_clks TEGRA194_CLK_MIPI_CAL>,
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<&bpmp_clks TEGRA194_CLK_MPHY_CORE_PLL_FIXED>,
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<&bpmp_clks TEGRA194_CLK_MPHY_L0_RX_ANA>,
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<&bpmp_clks TEGRA194_CLK_MPHY_L0_RX_LS_BIT>,
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<&bpmp_clks TEGRA194_CLK_MPHY_L0_RX_SYMB>,
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<&bpmp_clks TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT>,
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<&bpmp_clks TEGRA194_CLK_MPHY_L0_TX_SYMB>,
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<&bpmp_clks TEGRA194_CLK_MPHY_L1_RX_ANA>,
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<&bpmp_clks TEGRA194_CLK_MPHY_TX_1MHZ_REF>,
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<&bpmp_clks TEGRA194_CLK_NVCSI>,
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<&bpmp_clks TEGRA194_CLK_NVCSILP>,
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<&bpmp_clks TEGRA194_CLK_NVDEC>,
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<&bpmp_clks TEGRA194_CLK_NVDISPLAYHUB>,
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<&bpmp_clks TEGRA194_CLK_NVDISPLAY_DISP>,
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<&bpmp_clks TEGRA194_CLK_NVDISPLAY_P0>,
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<&bpmp_clks TEGRA194_CLK_NVDISPLAY_P1>,
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<&bpmp_clks TEGRA194_CLK_NVDISPLAY_P2>,
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<&bpmp_clks TEGRA194_CLK_NVENC>,
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<&bpmp_clks TEGRA194_CLK_NVJPG>,
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<&bpmp_clks TEGRA194_CLK_OSC>,
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<&bpmp_clks TEGRA194_CLK_AON_TOUCH>,
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<&bpmp_clks TEGRA194_CLK_PLLA>,
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<&bpmp_clks TEGRA194_CLK_PLLAON>,
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<&bpmp_clks TEGRA194_CLK_PLLD>,
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<&bpmp_clks TEGRA194_CLK_PLLD2>,
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<&bpmp_clks TEGRA194_CLK_PLLD3>,
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<&bpmp_clks TEGRA194_CLK_PLLDP>,
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<&bpmp_clks TEGRA194_CLK_PLLD4>,
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<&bpmp_clks TEGRA194_CLK_PLLE>,
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<&bpmp_clks TEGRA194_CLK_PLLP>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
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<&bpmp_clks TEGRA194_CLK_UTMIPLL>,
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<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
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<&bpmp_clks TEGRA194_CLK_PWM1>,
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<&bpmp_clks TEGRA194_CLK_PWM2>,
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<&bpmp_clks TEGRA194_CLK_PWM3>,
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<&bpmp_clks TEGRA194_CLK_PWM4>,
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<&bpmp_clks TEGRA194_CLK_PWM5>,
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<&bpmp_clks TEGRA194_CLK_PWM6>,
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<&bpmp_clks TEGRA194_CLK_PWM7>,
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<&bpmp_clks TEGRA194_CLK_PWM8>,
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<&bpmp_clks TEGRA194_CLK_RCE_CPU_NIC>,
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<&bpmp_clks TEGRA194_CLK_RCE_NIC>,
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<&bpmp_clks TEGRA194_CLK_SATA>,
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<&bpmp_clks TEGRA194_CLK_SATA_OOB>,
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<&bpmp_clks TEGRA194_CLK_AON_I2C_SLOW>,
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<&bpmp_clks TEGRA194_CLK_SCE_CPU_NIC>,
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<&bpmp_clks TEGRA194_CLK_SCE_NIC>,
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<&bpmp_clks TEGRA194_CLK_SDMMC1>,
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<&bpmp_clks TEGRA194_CLK_UPHY_PLL3>,
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<&bpmp_clks TEGRA194_CLK_SDMMC3>,
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<&bpmp_clks TEGRA194_CLK_SDMMC4>,
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<&bpmp_clks TEGRA194_CLK_SE>,
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<&bpmp_clks TEGRA194_CLK_SOR0_OUT>,
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<&bpmp_clks TEGRA194_CLK_SOR0_REF>,
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<&bpmp_clks TEGRA194_CLK_SOR0_PAD_CLKOUT>,
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<&bpmp_clks TEGRA194_CLK_SOR1_OUT>,
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<&bpmp_clks TEGRA194_CLK_SOR1_REF>,
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<&bpmp_clks TEGRA194_CLK_SOR1_PAD_CLKOUT>,
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<&bpmp_clks TEGRA194_CLK_SOR_SAFE>,
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<&bpmp_clks TEGRA194_CLK_IQC1_IN>,
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<&bpmp_clks TEGRA194_CLK_IQC2_IN>,
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<&bpmp_clks TEGRA194_CLK_DMIC5>,
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<&bpmp_clks TEGRA194_CLK_SPI1>,
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<&bpmp_clks TEGRA194_CLK_SPI2>,
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<&bpmp_clks TEGRA194_CLK_SPI3>,
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<&bpmp_clks TEGRA194_CLK_I2C_SLOW>,
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<&bpmp_clks TEGRA194_CLK_SYNC_DMIC1>,
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<&bpmp_clks TEGRA194_CLK_SYNC_DMIC2>,
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<&bpmp_clks TEGRA194_CLK_SYNC_DMIC3>,
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<&bpmp_clks TEGRA194_CLK_SYNC_DMIC4>,
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<&bpmp_clks TEGRA194_CLK_SYNC_DSPK1>,
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<&bpmp_clks TEGRA194_CLK_SYNC_DSPK2>,
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<&bpmp_clks TEGRA194_CLK_SYNC_I2S1>,
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<&bpmp_clks TEGRA194_CLK_SYNC_I2S2>,
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<&bpmp_clks TEGRA194_CLK_SYNC_I2S3>,
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<&bpmp_clks TEGRA194_CLK_SYNC_I2S4>,
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<&bpmp_clks TEGRA194_CLK_SYNC_I2S5>,
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<&bpmp_clks TEGRA194_CLK_SYNC_I2S6>,
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<&bpmp_clks TEGRA194_CLK_MPHY_FORCE_LS_MODE>,
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<&bpmp_clks TEGRA194_CLK_TACH>,
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<&bpmp_clks TEGRA194_CLK_TSEC>,
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<&bpmp_clks TEGRA194_CLK_TSECB>,
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<&bpmp_clks TEGRA194_CLK_UARTA>,
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<&bpmp_clks TEGRA194_CLK_UARTB>,
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<&bpmp_clks TEGRA194_CLK_UARTC>,
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<&bpmp_clks TEGRA194_CLK_UARTD>,
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<&bpmp_clks TEGRA194_CLK_UARTE>,
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<&bpmp_clks TEGRA194_CLK_UARTF>,
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<&bpmp_clks TEGRA194_CLK_UARTG>,
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<&bpmp_clks TEGRA194_CLK_UART_FST_MIPI_CAL>,
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<&bpmp_clks TEGRA194_CLK_UFSDEV_REF>,
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<&bpmp_clks TEGRA194_CLK_UFSHC>,
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<&bpmp_clks TEGRA194_CLK_USB2_TRK>,
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<&bpmp_clks TEGRA194_CLK_VI>,
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<&bpmp_clks TEGRA194_CLK_VIC>,
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<&bpmp_clks TEGRA194_CLK_PVA0_AXI>,
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<&bpmp_clks TEGRA194_CLK_PVA0_VPS0>,
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<&bpmp_clks TEGRA194_CLK_PVA0_VPS1>,
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<&bpmp_clks TEGRA194_CLK_PVA1_AXI>,
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<&bpmp_clks TEGRA194_CLK_PVA1_VPS0>,
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<&bpmp_clks TEGRA194_CLK_PVA1_VPS1>,
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<&bpmp_clks TEGRA194_CLK_DLA0_FALCON>,
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<&bpmp_clks TEGRA194_CLK_DLA0_CORE>,
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<&bpmp_clks TEGRA194_CLK_DLA1_FALCON>,
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<&bpmp_clks TEGRA194_CLK_DLA1_CORE>,
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<&bpmp_clks TEGRA194_CLK_SOR2_OUT>,
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<&bpmp_clks TEGRA194_CLK_SOR2_REF>,
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<&bpmp_clks TEGRA194_CLK_SOR2_PAD_CLKOUT>,
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<&bpmp_clks TEGRA194_CLK_SOR3_OUT>,
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<&bpmp_clks TEGRA194_CLK_SOR3_REF>,
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<&bpmp_clks TEGRA194_CLK_SOR3_PAD_CLKOUT>,
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<&bpmp_clks TEGRA194_CLK_NVDISPLAY_P3>,
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<&bpmp_clks TEGRA194_CLK_DPAUX2>,
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<&bpmp_clks TEGRA194_CLK_DPAUX3>,
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<&bpmp_clks TEGRA194_CLK_NVDEC1>,
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<&bpmp_clks TEGRA194_CLK_NVENC1>,
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<&bpmp_clks TEGRA194_CLK_SE_FREE>,
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<&bpmp_clks TEGRA194_CLK_UARTH>,
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<&bpmp_clks TEGRA194_CLK_FUSE_SERIAL>,
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<&bpmp_clks TEGRA194_CLK_QSPI0>,
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<&bpmp_clks TEGRA194_CLK_QSPI1>,
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<&bpmp_clks TEGRA194_CLK_QSPI0_PM>,
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<&bpmp_clks TEGRA194_CLK_QSPI1_PM>,
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<&bpmp_clks TEGRA194_CLK_VI_CONST>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_BPMP>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_SCE>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_NVDEC>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_NVJPG>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_TSEC>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_TSECB>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_VI>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_SE>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_NVENC>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_ISP>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_VIC>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_NVDISPLAYHUB>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_AXICBB>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_DLA>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_PVA_CORE>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_PVA_VPS>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_CVNAS>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_RCE>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_NVENC1>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_DLA_FALCON>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_NVDEC1>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_GPU>,
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<&bpmp_clks TEGRA194_CLK_SDMMC_LEGACY_TM>,
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<&bpmp_clks TEGRA194_CLK_PEX0_CORE_0>,
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<&bpmp_clks TEGRA194_CLK_PEX0_CORE_1>,
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<&bpmp_clks TEGRA194_CLK_PEX0_CORE_2>,
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<&bpmp_clks TEGRA194_CLK_PEX0_CORE_3>,
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<&bpmp_clks TEGRA194_CLK_PEX0_CORE_4>,
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<&bpmp_clks TEGRA194_CLK_PEX1_CORE_5>,
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<&bpmp_clks TEGRA194_CLK_PEX_REF1>,
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<&bpmp_clks TEGRA194_CLK_PEX_REF2>,
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<&bpmp_clks TEGRA194_CLK_NVHS_REF>,
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<&bpmp_clks TEGRA194_CLK_CSI_A>,
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<&bpmp_clks TEGRA194_CLK_CSI_B>,
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<&bpmp_clks TEGRA194_CLK_CSI_C>,
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<&bpmp_clks TEGRA194_CLK_CSI_D>,
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<&bpmp_clks TEGRA194_CLK_CSI_E>,
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<&bpmp_clks TEGRA194_CLK_CSI_F>,
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<&bpmp_clks TEGRA194_CLK_CSI_G>,
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<&bpmp_clks TEGRA194_CLK_CSI_H>,
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<&bpmp_clks TEGRA194_CLK_PLLC4>,
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<&bpmp_clks TEGRA194_CLK_PLLC4_OUT>,
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<&bpmp_clks TEGRA194_CLK_PLLC4_OUT1>,
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<&bpmp_clks TEGRA194_CLK_PLLC4_OUT2>,
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<&bpmp_clks TEGRA194_CLK_PLLC4_MUXED>,
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<&bpmp_clks TEGRA194_CLK_PLLC4_VCO_DIV2>,
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<&bpmp_clks TEGRA194_CLK_PLLNVHS>,
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<&bpmp_clks TEGRA194_CLK_CSI_A_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_B_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_C_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_D_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_E_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_F_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_G_PAD>,
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<&bpmp_clks TEGRA194_CLK_CSI_H_PAD>,
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<&bpmp_clks TEGRA194_CLK_SLVSEC>,
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<&bpmp_clks TEGRA194_CLK_SLVSEC_PADCTRL>,
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<&bpmp_clks TEGRA194_CLK_PEX_SATA_USB_RX_BYP>,
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<&bpmp_clks TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT>,
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<&bpmp_clks TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT>,
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<&bpmp_clks TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT>,
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<&bpmp_clks TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT>,
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<&bpmp_clks TEGRA194_CLK_NVLINK_SYS>,
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<&bpmp_clks TEGRA194_CLK_NVLINK_RX>,
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<&bpmp_clks TEGRA194_CLK_NVLINK_TX>,
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<&bpmp_clks TEGRA194_CLK_NVLINK_TX_DIV>,
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<&bpmp_clks TEGRA194_CLK_NVHS_RX_BYP_REF>,
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<&bpmp_clks TEGRA194_CLK_NVHS_PLL0_MGMT>,
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<&bpmp_clks TEGRA194_CLK_XUSB_CORE_DEV>,
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<&bpmp_clks TEGRA194_CLK_XUSB_CORE_MUX>,
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<&bpmp_clks TEGRA194_CLK_XUSB_CORE_HOST>,
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<&bpmp_clks TEGRA194_CLK_XUSB_CORE_SS>,
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<&bpmp_clks TEGRA194_CLK_XUSB_FALCON>,
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<&bpmp_clks TEGRA194_CLK_XUSB_FALCON_HOST>,
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<&bpmp_clks TEGRA194_CLK_XUSB_FALCON_SS>,
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<&bpmp_clks TEGRA194_CLK_XUSB_FS>,
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<&bpmp_clks TEGRA194_CLK_XUSB_FS_HOST>,
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<&bpmp_clks TEGRA194_CLK_XUSB_FS_DEV>,
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<&bpmp_clks TEGRA194_CLK_XUSB_SS>,
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<&bpmp_clks TEGRA194_CLK_XUSB_SS_DEV>,
|
|
<&bpmp_clks TEGRA194_CLK_XUSB_SS_SUPERSPEED>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLDISPHUB>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLDISPHUB_DIV>,
|
|
<&bpmp_clks TEGRA194_CLK_NAFLL_CLUSTER0>,
|
|
<&bpmp_clks TEGRA194_CLK_NAFLL_CLUSTER1>,
|
|
<&bpmp_clks TEGRA194_CLK_NAFLL_CLUSTER2>,
|
|
<&bpmp_clks TEGRA194_CLK_NAFLL_CLUSTER3>,
|
|
<&bpmp_clks TEGRA194_CLK_CAN1_CORE>,
|
|
<&bpmp_clks TEGRA194_CLK_CAN2_CORE>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLA1_OUT1>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLNVHS_HPS>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLREFE_VCOOUT>,
|
|
<&bpmp_clks TEGRA194_CLK_CLK_32K>,
|
|
<&bpmp_clks TEGRA194_CLK_SPDIFIN_SYNC_INPUT>,
|
|
<&bpmp_clks TEGRA194_CLK_UTMIPLL_CLKOUT48>,
|
|
<&bpmp_clks TEGRA194_CLK_UTMIPLL_CLKOUT480>,
|
|
<&bpmp_clks TEGRA194_CLK_CVNAS>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLNVCSI>,
|
|
<&bpmp_clks TEGRA194_CLK_PVA0_CPU_AXI>,
|
|
<&bpmp_clks TEGRA194_CLK_PVA1_CPU_AXI>,
|
|
<&bpmp_clks TEGRA194_CLK_PVA0_VPS>,
|
|
<&bpmp_clks TEGRA194_CLK_PVA1_VPS>,
|
|
<&bpmp_clks TEGRA194_CLK_DLA0_FALCON_MUX>,
|
|
<&bpmp_clks TEGRA194_CLK_DLA1_FALCON_MUX>,
|
|
<&bpmp_clks TEGRA194_CLK_DLA0_CORE_MUX>,
|
|
<&bpmp_clks TEGRA194_CLK_DLA1_CORE_MUX>,
|
|
<&bpmp_clks TEGRA194_CLK_UTMIPLL_HPS>,
|
|
<&bpmp_clks TEGRA194_CLK_I2C5>,
|
|
<&bpmp_clks TEGRA194_CLK_I2C10>,
|
|
<&bpmp_clks TEGRA194_CLK_BPMP_CPU_NIC>,
|
|
<&bpmp_clks TEGRA194_CLK_BPMP_APB>,
|
|
<&bpmp_clks TEGRA194_CLK_TSC>,
|
|
<&bpmp_clks TEGRA194_CLK_EMCSA>,
|
|
<&bpmp_clks TEGRA194_CLK_EMCSB>,
|
|
<&bpmp_clks TEGRA194_CLK_EMCSC>,
|
|
<&bpmp_clks TEGRA194_CLK_EMCSD>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLC>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLC2>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLC3>,
|
|
<&bpmp_clks TEGRA194_CLK_PLLE_HPS>;
|
|
clock-names = "actmon",
|
|
"adsp",
|
|
"adspneon",
|
|
"ahub",
|
|
"apb2ape",
|
|
"ape",
|
|
"aud_mclk",
|
|
"axi_cbb",
|
|
"can1",
|
|
"can1_host",
|
|
"can2",
|
|
"can2_host",
|
|
"cec",
|
|
"clk_m",
|
|
"dmic1",
|
|
"dmic2",
|
|
"dmic3",
|
|
"dmic4",
|
|
"dpaux",
|
|
"dpaux1",
|
|
"aclk",
|
|
"mss_encrypt",
|
|
"eqos_rx_input",
|
|
"icq2",
|
|
"aon_apb",
|
|
"aon_nic",
|
|
"aon_cpu_nic",
|
|
"plla1",
|
|
"dspk1",
|
|
"dspk2",
|
|
"emc",
|
|
"eqos_axi",
|
|
"eqos_ptp_ref",
|
|
"eqos_rx",
|
|
"eqos_tx",
|
|
"extperiph1",
|
|
"extperiph2",
|
|
"extperiph3",
|
|
"extperiph4",
|
|
"fuse",
|
|
"gpcclk",
|
|
"gpu_pwr",
|
|
"hda",
|
|
"hda2codec_2x",
|
|
"hda2hdmicodec",
|
|
"host1x",
|
|
"hsic_trk",
|
|
"i2c1",
|
|
"i2c2",
|
|
"i2c3",
|
|
"i2c4",
|
|
"i2c6",
|
|
"i2c7",
|
|
"i2c8",
|
|
"i2c9",
|
|
"i2s1",
|
|
"i2s1_sync_input",
|
|
"i2s2",
|
|
"i2s2_sync_input",
|
|
"i2s3",
|
|
"i2s3_sync_input",
|
|
"i2s4",
|
|
"i2s4_sync_input",
|
|
"i2s5",
|
|
"i2s5_sync_input",
|
|
"i2s6",
|
|
"i2s6_sync_input",
|
|
"iqc1",
|
|
"isp",
|
|
"kfuse",
|
|
"maud",
|
|
"mipi_cal",
|
|
"mphy_core_pll_fixed",
|
|
"mphy_l0_rx_ana",
|
|
"mphy_l0_rx_ls_bit",
|
|
"mphy_l0_rx_symb",
|
|
"mphy_l0_tx_ls_3xbit",
|
|
"mphy_l0_tx_symb",
|
|
"mphy_l1_rx_ana",
|
|
"mphy_tx_1mhz_ref",
|
|
"nvcsi",
|
|
"nvcsilp",
|
|
"nvdec",
|
|
"nvdisplayhub",
|
|
"nvdisplay_disp",
|
|
"nvdisplay_p0",
|
|
"nvdisplay_p1",
|
|
"nvdisplay_p2",
|
|
"nvenc",
|
|
"nvjpg",
|
|
"osc",
|
|
"aon_touch",
|
|
"plla",
|
|
"pllaon",
|
|
"plld",
|
|
"plld2",
|
|
"plld3",
|
|
"plldp",
|
|
"plld4",
|
|
"plle",
|
|
"pllp",
|
|
"pllp_out0",
|
|
"utmipll",
|
|
"plla_out0",
|
|
"pwm1",
|
|
"pwm2",
|
|
"pwm3",
|
|
"pwm4",
|
|
"pwm5",
|
|
"pwm6",
|
|
"pwm7",
|
|
"pwm8",
|
|
"rce_cpu_nic",
|
|
"rce_nic",
|
|
"sata",
|
|
"sata_oob",
|
|
"aon_i2c_slow",
|
|
"sce_cpu_nic",
|
|
"sce_nic",
|
|
"sdmmc1",
|
|
"uphy_pll3",
|
|
"sdmmc3",
|
|
"sdmmc4",
|
|
"se",
|
|
"sor0_out",
|
|
"sor0_ref",
|
|
"sor0_pad_clkout",
|
|
"sor1_out",
|
|
"sor1_ref",
|
|
"sor1_pad_clkout",
|
|
"sor_safe",
|
|
"iqc1_in",
|
|
"iqc2_in",
|
|
"dmic5",
|
|
"spi1",
|
|
"spi2",
|
|
"spi3",
|
|
"i2c_slow",
|
|
"sync_dmic1",
|
|
"sync_dmic2",
|
|
"sync_dmic3",
|
|
"sync_dmic4",
|
|
"sync_dspk1",
|
|
"sync_dspk2",
|
|
"sync_i2s1",
|
|
"sync_i2s2",
|
|
"sync_i2s3",
|
|
"sync_i2s4",
|
|
"sync_i2s5",
|
|
"sync_i2s6",
|
|
"mphy_force_ls_mode",
|
|
"tach",
|
|
"tsec",
|
|
"tsecb",
|
|
"uarta",
|
|
"uartb",
|
|
"uartc",
|
|
"uartd",
|
|
"uarte",
|
|
"uartf",
|
|
"uartg",
|
|
"uart_fst_mipi_cal",
|
|
"ufsdev_ref",
|
|
"ufshc",
|
|
"usb2_trk",
|
|
"vi",
|
|
"vic",
|
|
"pva0_axi",
|
|
"pva0_vps0",
|
|
"pva0_vps1",
|
|
"pva1_axi",
|
|
"pva1_vps0",
|
|
"pva1_vps1",
|
|
"dla0_falcon",
|
|
"dla0_core",
|
|
"dla1_falcon",
|
|
"dla1_core",
|
|
"sor2_out",
|
|
"sor2_ref",
|
|
"sor2_pad_clkout",
|
|
"sor3_out",
|
|
"sor3_ref",
|
|
"sor3_pad_clkout",
|
|
"nvdisplay_p3",
|
|
"dpaux2",
|
|
"dpaux3",
|
|
"nvdec1",
|
|
"nvenc1",
|
|
"se_free",
|
|
"uarth",
|
|
"fuse_serial",
|
|
"qspi0",
|
|
"qspi1",
|
|
"qspi0_pm",
|
|
"qspi1_pm",
|
|
"vi_const",
|
|
"nafll_bpmp",
|
|
"nafll_sce",
|
|
"nafll_nvdec",
|
|
"nafll_nvjpg",
|
|
"nafll_tsec",
|
|
"nafll_tsecb",
|
|
"nafll_vi",
|
|
"nafll_se",
|
|
"nafll_nvenc",
|
|
"nafll_isp",
|
|
"nafll_vic",
|
|
"nafll_nvdisplayhub",
|
|
"nafll_axicbb",
|
|
"nafll_dla",
|
|
"nafll_pva_core",
|
|
"nafll_pva_vps",
|
|
"nafll_cvnas",
|
|
"nafll_rce",
|
|
"nafll_nvenc1",
|
|
"nafll_dla_falcon",
|
|
"nafll_nvdec1",
|
|
"nafll_gpu",
|
|
"sdmmc_legacy_tm",
|
|
"pex0_core_0",
|
|
"pex0_core_1",
|
|
"pex0_core_2",
|
|
"pex0_core_3",
|
|
"pex0_core_4",
|
|
"pex1_core_5",
|
|
"pex_ref1",
|
|
"pex_ref2",
|
|
"nvhs_ref",
|
|
"csi_a",
|
|
"csi_b",
|
|
"csi_c",
|
|
"csi_d",
|
|
"csi_e",
|
|
"csi_f",
|
|
"csi_g",
|
|
"csi_h",
|
|
"pllc4",
|
|
"pllc4_out",
|
|
"pllc4_out1",
|
|
"pllc4_out2",
|
|
"pllc4_muxed",
|
|
"pllc4_vco_div2",
|
|
"pllnvhs",
|
|
"csi_a_pad",
|
|
"csi_b_pad",
|
|
"csi_c_pad",
|
|
"csi_d_pad",
|
|
"csi_e_pad",
|
|
"csi_f_pad",
|
|
"csi_g_pad",
|
|
"csi_h_pad",
|
|
"slvsec",
|
|
"slvsec_padctrl",
|
|
"pex_sata_usb_rx_byp",
|
|
"pex_usb_pad_pll0_mgmt",
|
|
"pex_usb_pad_pll1_mgmt",
|
|
"pex_usb_pad_pll2_mgmt",
|
|
"pex_usb_pad_pll3_mgmt",
|
|
"nvlink_sys",
|
|
"nvlink_rx",
|
|
"nvlink_tx",
|
|
"nvlink_tx_div",
|
|
"nvhs_rx_byp_ref",
|
|
"nvhs_pll0_mgmt",
|
|
"xusb_core_dev",
|
|
"xusb_core_mux",
|
|
"xusb_core_host",
|
|
"xusb_core_ss",
|
|
"xusb_falcon",
|
|
"xusb_falcon_host",
|
|
"xusb_falcon_ss",
|
|
"xusb_fs",
|
|
"xusb_fs_host",
|
|
"xusb_fs_dev",
|
|
"xusb_ss",
|
|
"xusb_ss_dev",
|
|
"xusb_ss_superspeed",
|
|
"plldisphub",
|
|
"plldisphub_div",
|
|
"nafll_cluster0",
|
|
"nafll_cluster1",
|
|
"nafll_cluster2",
|
|
"nafll_cluster3",
|
|
"can1_core",
|
|
"can2_core",
|
|
"plla1_out1",
|
|
"pllnvhs_hps",
|
|
"pllrefe_vcoout",
|
|
"clk_32k",
|
|
"spdifin_sync_input",
|
|
"utmipll_clkout48",
|
|
"utmipll_clkout480",
|
|
"cvnas",
|
|
"pllnvcsi",
|
|
"pva0_cpu_axi",
|
|
"pva1_cpu_axi",
|
|
"pva0_vps",
|
|
"pva1_vps",
|
|
"dla0_falcon_mux",
|
|
"dla1_falcon_mux",
|
|
"dla0_core_mux",
|
|
"dla1_core_mux",
|
|
"utmipll_hps",
|
|
"i2c5",
|
|
"i2c10",
|
|
"bpmp_cpu_nic",
|
|
"bpmp_apb",
|
|
"tsc",
|
|
"emcsa",
|
|
"emcsb",
|
|
"emcsc",
|
|
"emcsd",
|
|
"pll_c",
|
|
"pll_c2",
|
|
"pll_c3",
|
|
"plle_hps";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_ACTMON>,
|
|
<&bpmp_resets TEGRA194_RESET_ADSP_ALL>,
|
|
<&bpmp_resets TEGRA194_RESET_AFI>,
|
|
<&bpmp_resets TEGRA194_RESET_CAN1>,
|
|
<&bpmp_resets TEGRA194_RESET_CAN2>,
|
|
<&bpmp_resets TEGRA194_RESET_DLA0>,
|
|
<&bpmp_resets TEGRA194_RESET_DLA1>,
|
|
<&bpmp_resets TEGRA194_RESET_DPAUX>,
|
|
<&bpmp_resets TEGRA194_RESET_DPAUX1>,
|
|
<&bpmp_resets TEGRA194_RESET_DPAUX2>,
|
|
<&bpmp_resets TEGRA194_RESET_DPAUX3>,
|
|
<&bpmp_resets TEGRA194_RESET_EQOS>,
|
|
<&bpmp_resets TEGRA194_RESET_GPCDMA>,
|
|
<&bpmp_resets TEGRA194_RESET_GPU>,
|
|
<&bpmp_resets TEGRA194_RESET_HDA>,
|
|
<&bpmp_resets TEGRA194_RESET_HDA2CODEC_2X>,
|
|
<&bpmp_resets TEGRA194_RESET_HDA2HDMICODEC>,
|
|
<&bpmp_resets TEGRA194_RESET_HOST1X>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C1>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C10>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C2>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C3>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C4>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C6>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C7>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C8>,
|
|
<&bpmp_resets TEGRA194_RESET_I2C9>,
|
|
<&bpmp_resets TEGRA194_RESET_ISP>,
|
|
<&bpmp_resets TEGRA194_RESET_MIPI_CAL>,
|
|
<&bpmp_resets TEGRA194_RESET_MPHY_CLK_CTL>,
|
|
<&bpmp_resets TEGRA194_RESET_MPHY_L0_RX>,
|
|
<&bpmp_resets TEGRA194_RESET_MPHY_L0_TX>,
|
|
<&bpmp_resets TEGRA194_RESET_MPHY_L1_RX>,
|
|
<&bpmp_resets TEGRA194_RESET_MPHY_L1_TX>,
|
|
<&bpmp_resets TEGRA194_RESET_NVCSI>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDEC>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_HEAD0>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_HEAD1>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_HEAD2>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_HEAD3>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_MISC>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_WGRP0>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_WGRP1>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_WGRP2>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_WGRP3>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_WGRP4>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDISPLAY0_WGRP5>,
|
|
<&bpmp_resets TEGRA194_RESET_NVENC>,
|
|
<&bpmp_resets TEGRA194_RESET_NVENC1>,
|
|
<&bpmp_resets TEGRA194_RESET_NVJPG>,
|
|
<&bpmp_resets TEGRA194_RESET_PCIE>,
|
|
<&bpmp_resets TEGRA194_RESET_PCIEXCLK>,
|
|
<&bpmp_resets TEGRA194_RESET_PVA0_ALL>,
|
|
<&bpmp_resets TEGRA194_RESET_PVA1_ALL>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM1>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM2>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM3>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM4>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM5>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM6>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM7>,
|
|
<&bpmp_resets TEGRA194_RESET_PWM8>,
|
|
<&bpmp_resets TEGRA194_RESET_QSPI0>,
|
|
<&bpmp_resets TEGRA194_RESET_QSPI1>,
|
|
<&bpmp_resets TEGRA194_RESET_SATA>,
|
|
<&bpmp_resets TEGRA194_RESET_SATACOLD>,
|
|
<&bpmp_resets TEGRA194_RESET_SCE_ALL>,
|
|
<&bpmp_resets TEGRA194_RESET_RCE_ALL>,
|
|
<&bpmp_resets TEGRA194_RESET_SDMMC1>,
|
|
<&bpmp_resets TEGRA194_RESET_SDMMC3>,
|
|
<&bpmp_resets TEGRA194_RESET_SDMMC4>,
|
|
<&bpmp_resets TEGRA194_RESET_SE>,
|
|
<&bpmp_resets TEGRA194_RESET_SOR0>,
|
|
<&bpmp_resets TEGRA194_RESET_SOR1>,
|
|
<&bpmp_resets TEGRA194_RESET_SOR2>,
|
|
<&bpmp_resets TEGRA194_RESET_SOR3>,
|
|
<&bpmp_resets TEGRA194_RESET_SPI1>,
|
|
<&bpmp_resets TEGRA194_RESET_SPI2>,
|
|
<&bpmp_resets TEGRA194_RESET_SPI3>,
|
|
<&bpmp_resets TEGRA194_RESET_SPI4>,
|
|
<&bpmp_resets TEGRA194_RESET_TACH>,
|
|
<&bpmp_resets TEGRA194_RESET_TSCTNVI>,
|
|
<&bpmp_resets TEGRA194_RESET_TSEC>,
|
|
<&bpmp_resets TEGRA194_RESET_TSECB>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTA>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTB>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTC>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTD>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTE>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTF>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTG>,
|
|
<&bpmp_resets TEGRA194_RESET_UARTH>,
|
|
<&bpmp_resets TEGRA194_RESET_UFSHC>,
|
|
<&bpmp_resets TEGRA194_RESET_UFSHC_AXI_M>,
|
|
<&bpmp_resets TEGRA194_RESET_UFSHC_LP_SEQ>,
|
|
<&bpmp_resets TEGRA194_RESET_VI>,
|
|
<&bpmp_resets TEGRA194_RESET_VIC>,
|
|
<&bpmp_resets TEGRA194_RESET_XUSB_PADCTL>,
|
|
<&bpmp_resets TEGRA194_RESET_NVDEC1>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_0>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_1>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_2>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_3>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_4>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_0_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_1_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_2_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_3_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_4_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_COMMON_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_SLVSEC>,
|
|
<&bpmp_resets TEGRA194_RESET_NVLINK>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX1_CORE_5>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX1_CORE_5_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_CVNAS>,
|
|
<&bpmp_resets TEGRA194_RESET_CVNAS_FCM>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_PLL0>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L0>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L1>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L2>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L3>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L4>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L5>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L6>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_L7>,
|
|
<&bpmp_resets TEGRA194_RESET_NVHS_UPHY_PM>,
|
|
<&bpmp_resets TEGRA194_RESET_DMIC5>,
|
|
<&bpmp_resets TEGRA194_RESET_APE>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L0>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L1>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L2>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L3>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L4>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L5>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L6>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L7>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L8>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L9>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L10>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_L11>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_PLL0>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_PLL1>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_PLL2>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX_USB_UPHY_PLL3>;
|
|
reset-names = "actmon",
|
|
"adsp_all",
|
|
"afi",
|
|
"can1",
|
|
"can2",
|
|
"dla0",
|
|
"dla1",
|
|
"dpaux",
|
|
"dpaux1",
|
|
"dpaux2",
|
|
"dpaux3",
|
|
"eqos",
|
|
"gpcdma",
|
|
"gpu",
|
|
"hda",
|
|
"hda2codec_2x",
|
|
"hda2hdmicodec",
|
|
"host1x",
|
|
"i2c1",
|
|
"i2c10",
|
|
"i2c2",
|
|
"i2c3",
|
|
"i2c4",
|
|
"i2c6",
|
|
"i2c7",
|
|
"i2c8",
|
|
"i2c9",
|
|
"isp",
|
|
"mipi_cal",
|
|
"mphy_clk_ctl",
|
|
"mphy_l0_rx",
|
|
"mphy_l0_tx",
|
|
"mphy_l1_rx",
|
|
"mphy_l1_tx",
|
|
"nvcsi",
|
|
"nvdec",
|
|
"nvdisplay0_head0",
|
|
"nvdisplay0_head1",
|
|
"nvdisplay0_head2",
|
|
"nvdisplay0_head3",
|
|
"nvdisplay0_misc",
|
|
"nvdisplay0_wgrp0",
|
|
"nvdisplay0_wgrp1",
|
|
"nvdisplay0_wgrp2",
|
|
"nvdisplay0_wgrp3",
|
|
"nvdisplay0_wgrp4",
|
|
"nvdisplay0_wgrp5",
|
|
"nvenc",
|
|
"nvenc1",
|
|
"nvjpg",
|
|
"pcie",
|
|
"pciexclk",
|
|
"pva0_all",
|
|
"pva1_all",
|
|
"pwm1",
|
|
"pwm2",
|
|
"pwm3",
|
|
"pwm4",
|
|
"pwm5",
|
|
"pwm6",
|
|
"pwm7",
|
|
"pwm8",
|
|
"qspi0",
|
|
"qspi1",
|
|
"sata",
|
|
"satacold",
|
|
"sce_all",
|
|
"rce_all",
|
|
"sdmmc1",
|
|
"sdmmc3",
|
|
"sdmmc4",
|
|
"se",
|
|
"sor0",
|
|
"sor1",
|
|
"sor2",
|
|
"sor3",
|
|
"spi1",
|
|
"spi2",
|
|
"spi3",
|
|
"spi4",
|
|
"tach",
|
|
"tsctnvi",
|
|
"tsec",
|
|
"tsecb",
|
|
"uarta",
|
|
"uartb",
|
|
"uartc",
|
|
"uartd",
|
|
"uarte",
|
|
"uartf",
|
|
"uartg",
|
|
"uarth",
|
|
"ufshc",
|
|
"ufshc_axi_m",
|
|
"ufshc_lp_seq",
|
|
"vi",
|
|
"vic",
|
|
"xusb_padctl",
|
|
"nvdec1",
|
|
"pex0_core_0",
|
|
"pex0_core_1",
|
|
"pex0_core_2",
|
|
"pex0_core_3",
|
|
"pex0_core_4",
|
|
"pex0_core_0_apb",
|
|
"pex0_core_1_apb",
|
|
"pex0_core_2_apb",
|
|
"pex0_core_3_apb",
|
|
"pex0_core_4_apb",
|
|
"pex0_common_apb",
|
|
"slvsec",
|
|
"nvlink",
|
|
"pex1_core_5",
|
|
"pex1_core_5_apb",
|
|
"cvnas",
|
|
"cvnas_fcm",
|
|
"nvhs_uphy",
|
|
"nvhs_uphy_pll0",
|
|
"nvhs_uphy_l0",
|
|
"nvhs_uphy_l1",
|
|
"nvhs_uphy_l2",
|
|
"nvhs_uphy_l3",
|
|
"nvhs_uphy_l4",
|
|
"nvhs_uphy_l5",
|
|
"nvhs_uphy_l6",
|
|
"nvhs_uphy_l7",
|
|
"nvhs_uphy_pm",
|
|
"dmic5",
|
|
"ape",
|
|
"pex_usb_uphy",
|
|
"pex_usb_uphy_l0",
|
|
"pex_usb_uphy_l1",
|
|
"pex_usb_uphy_l2",
|
|
"pex_usb_uphy_l3",
|
|
"pex_usb_uphy_l4",
|
|
"pex_usb_uphy_l5",
|
|
"pex_usb_uphy_l6",
|
|
"pex_usb_uphy_l7",
|
|
"pex_usb_uphy_l8",
|
|
"pex_usb_uphy_l9",
|
|
"pex_usb_uphy_l10",
|
|
"pex_usb_uphy_l11",
|
|
"pex_usb_uphy_pll0",
|
|
"pex_usb_uphy_pll1",
|
|
"pex_usb_uphy_pll2",
|
|
"pex_usb_uphy_pll3";
|
|
};
|
|
};
|
|
};
|
|
|