forked from rrcarlosr/Jetpack
184 lines
5.5 KiB
Plaintext
184 lines
5.5 KiB
Plaintext
/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "tegra186-pin-drive-sdmmc-common.dtsi"
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/ {
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aliases {
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sdhci0 = &sdmmc1;
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sdhci1 = &sdmmc2;
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sdhci2 = &sdmmc3;
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sdhci3 = &sdmmc4;
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};
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sdmmc4: sdhci@3460000 { /* Used for eMMC */
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x3460000 0x0 0x210>;
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interrupts = < 0 65 0x04>;
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max-clk-limit = <196249804>;
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ddr-clk-limit = <48000000>;
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nvidia,clk-en-before-freq-update;
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tap-delay = <9>;
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trim-delay = <5>;
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nvidia,ddr-tap-delay = <9>;
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ddr-trim-delay = <5>;
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mmc-ocr-mask = <0>;
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bus-width = <8>;
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ignore-pm-notify;
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keep-power-in-suspend;
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non-removable;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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only-1-8-v;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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nvidia,min-tap-delay = <84>;
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nvidia,max-tap-delay = <136>;
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nvidia,is-emmc;
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nvidia,set-parent-clk;
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calib-3v3-offsets = <0x0505>;
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calib-1v8-offsets = <0x0505>;
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nvidia,parent_clk_list ="pll_p", "pll_p", "pll_p", "pll_p", "pll_p", "pll_c4_out0", "pll_c4_out0", "pll_c4_out0", "pll_c4_out0", "pll_c4_out0", "pll_c4_out0";
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pll_source = "pll_p", "pll_c4_out0";
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resets = <&tegra_car TEGRA186_RESET_SDMMC4>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA186_CLK_SDMMC4>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>,
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<&tegra_car TEGRA186_CLK_PLLC4_OUT0>,
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<&tegra_car TEGRA186_CLK_SDMMC_LEGACY_TM>;
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clock-names = "sdmmc", "pll_p", "pll_c4_out0", "sdmmc_legacy_tm";
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iommus = <&smmu TEGRA_SID_SDMMC4A>;
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status = "disabled";
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};
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sdmmc3: sdhci@3440000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x3440000 0x0 0x210>;
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interrupts = < 0 64 0x04>;
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max-clk-limit = <204000000>;
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ddr-clk-limit = <48000000>;
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tap-delay = <11>;
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trim-delay = <5>;
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nvidia,ddr-tap-delay = <11>;
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ddr-trim-delay = <5>;
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bus-width = <4>;
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ignore-pm-notify;
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mmc-ocr-mask = <0>;
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keep-power-in-suspend;
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non-removable;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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pwrdet-support;
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pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
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pinctrl-0 = <&sdmmc3_e_33V_enable>;
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pinctrl-1 = <&sdmmc3_e_33V_disable>;
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compad-vref-3v3 = <0x1>;
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compad-vref-1v8 = <0x2>;
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nvidia,min-tap-delay = <84>;
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nvidia,max-tap-delay = <136>;
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pll_source = "pll_p";
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resets = <&tegra_car TEGRA186_RESET_SDMMC3>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA186_CLK_SDMMC3>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>,
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<&tegra_car TEGRA186_CLK_SDMMC_LEGACY_TM>;
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clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
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iommus = <&smmu TEGRA_SID_SDMMC3A>;
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nvidia,en-periodic-calib;
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force-non-removable-rescan;
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status = "disabled";
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};
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sdmmc2: sdhci@3420000 { /* Should be used for eMMC. HS400 mode is not supported */
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x3420000 0x0 0x210>;
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interrupts = < 0 63 0x04>;
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max-clk-limit = <200000000>;
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ddr-clk-limit = <48000000>;
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tap-delay = <11>;
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trim-delay = <5>;
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nvidia,ddr-tap-delay = <11>;
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ddr-trim-delay = <5>;
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mmc-ocr-mask = <0>;
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bus-width = <8>;
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ignore-pm-notify;
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keep-power-in-suspend;
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non-removable;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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pwrdet-support;
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pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
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pinctrl-0 = <&sdmmc2_e_33V_enable>;
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pinctrl-1 = <&sdmmc2_e_33V_disable>;
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compad-vref-3v3 = <0x1>;
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compad-vref-1v8 = <0x2>;
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nvidia,is-emmc;
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nvidia,min-tap-delay = <84>;
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nvidia,max-tap-delay = <136>;
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pll_source = "pll_p";
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resets = <&tegra_car TEGRA186_RESET_SDMMC2>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA186_CLK_SDMMC2>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>,
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<&tegra_car TEGRA186_CLK_SDMMC_LEGACY_TM>;
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clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
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iommus = <&smmu TEGRA_SID_SDMMC2A>;
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status = "disabled";
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};
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sdmmc1: sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x3400000 0x0 0x210>;
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interrupts = < 0 62 0x04>;
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max-clk-limit = <204000000>;
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ddr-clk-limit = <48000000>;
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tap-delay = <11>;
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trim-delay = <5>;
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nvidia,ddr-tap-delay = <11>;
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ddr-trim-delay = <5>;
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mmc-ocr-mask = <3>;
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bus-width = <4>;
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ignore-pm-notify;
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keep-power-in-suspend;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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pwrdet-support;
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pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
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pinctrl-0 = <&sdmmc1_e_33V_enable>;
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pinctrl-1 = <&sdmmc1_e_33V_disable>;
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compad-vref-3v3 = <0x1>;
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compad-vref-1v8 = <0x2>;
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nvidia,min-tap-delay = <84>;
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nvidia,max-tap-delay = <136>;
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pll_source = "pll_p";
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resets = <&tegra_car TEGRA186_RESET_SDMMC1>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA186_CLK_SDMMC1>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>,
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<&tegra_car TEGRA186_CLK_SDMMC_LEGACY_TM>;
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clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
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iommus = <&smmu TEGRA_SID_SDMMC1A>;
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nvidia,en-periodic-calib;
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status = "disabled";
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};
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};
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