forked from rrcarlosr/Jetpack
328 lines
8.9 KiB
Plaintext
328 lines
8.9 KiB
Plaintext
/*
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* tegra186-camera.dtsi: Camera RTCPU DTSI file.
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*
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* Copyright (c) 2015-2017 NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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/ {
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aliases { /* SCE is the default Camera RTCPU */
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tegra-camera-rtcpu = &tegra_sce;
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};
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tegra_sce: rtcpu@b000000 {
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compatible = "nvidia,tegra186-sce-ivc";
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status = "disabled";
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reg = <0 0xb000000 0 0x1000>, /* SCE EVP (SCE_ATCM_EVP) */
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<0 0xb1f0000 0 0x40000>, /* SCE PM */
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<0 0xb230000 0 0x10000>, /* APS_FRSC (SCE_CFG) */
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<0 0xb040000 0 0x10000>,
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<0 0xb050000 0 0x10000>;
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reg-names = "sce-evp", "sce-pm", "sce-cfg",
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"ast-cpu", "ast-dma";
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iommus = <&smmu TEGRA_SID_RCE>;
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iommu-resv-regions = <0x0 0x0 0x0 0xA0000000 0x0 0xc0000000 0xffffffff 0xffffffff>;
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clocks =
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<&tegra_car TEGRA186_CLK_SCE_APB>,
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<&tegra_car TEGRA186_CLK_SCE_CPU_NIC>;
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clock-names = "sce-apb", "sce-cpu-nic";
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nvidia,clock-rates =
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<102000000 102000000>,
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<115200000 473600000>;
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resets =
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<&tegra_car TEGRA186_RESET_TSCTNSCE>,
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<&tegra_car TEGRA186_RESET_SCE_PM>,
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<&tegra_car TEGRA186_RESET_SCE_DBGRESETN>,
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<&tegra_car TEGRA186_RESET_SCE_PRESETDBGN>,
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<&tegra_car TEGRA186_RESET_SCE_ACTMON>,
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<&tegra_car TEGRA186_RESET_SCE_DMA>,
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<&tegra_car TEGRA186_RESET_SCE_TKE>,
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<&tegra_car TEGRA186_RESET_SCE_GTE>,
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<&tegra_car TEGRA186_RESET_SCE_CFG>,
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<&tegra_car TEGRA186_RESET_SCE_NRESET>,
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<&tegra_car TEGRA186_RESET_SCE_NSYSPORESET>;
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reset-names =
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"tsctnsce",
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"sce-pm",
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"sce-dbgresetn",
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"sce-presetdbgn",
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"sce-actmon",
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"sce-dma",
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"sce-tke",
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"sce-gte",
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"sce-cfg",
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"sce-nreset",
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"sce-nsysporeset";
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nvidia,reset-group-1 =
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"tsctnsce",
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"sce-pm",
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"sce-dbgresetn",
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"sce-presetdbgn",
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"sce-actmon",
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"sce-dma",
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"sce-tke",
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"sce-gte",
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"sce-cfg";
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nvidia,reset-group-2 =
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"sce-nreset",
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"sce-nsysporeset";
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/* Max EMC bandwidth used during initializing SCE */
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nvidia,memory-bw = <0xffffffff>;
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interrupts = <0 16 0x4>;
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interrupt-names = "wdt-remote";
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nvidia,trace = <&tegra_rtcpu_sce_trace 4 0x70100000 0x100000>;
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nvidia,ivc-channels = <&tegra_sce_ivc 2 0x90000000 0x10000>;
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nvidia,autosuspend-delay-ms = <5000>;
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hsp {
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compatible = "nvidia,tegra186-hsp-mailbox";
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nvidia,hsp-shared-mailbox = <&sce_hsp 1 &sce_hsp 6>;
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nvidia,hsp-shared-mailbox-names = "ivc-pair", "cmd-pair";
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};
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};
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tegra_rtcpu_sce_trace: tegra-rtcpu-sce-trace {
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nvidia,enable-printk;
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nvidia,interval-ms = <50>;
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nvidia,log-prefix = "[SCE]";
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};
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tegra_sce_ivc: sce-ivc-channels {
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echo@0 {
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compatible = "nvidia,tegra-ivc-cdev";
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nvidia,devname = "camchar-echo";
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nvidia,service = "echo";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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i2c@480 {
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compatible = "nvidia,tegra186-camera-ivc-rpc-i2c-single";
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nvidia,service = "i2c-single";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <8>;
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nvidia,frame-size = <128>;
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device = <&cam_i2c>;
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status = "disabled";
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};
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vinotify@12c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-vinotify";
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nvidia,service = "vinotify";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <64>;
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nvidia,frame-size = <128>;
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device = <&tegra_vi>;
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};
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mods@32c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-mods";
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nvidia,service = "mods";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <64>;
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};
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ivccontrol@52c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
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nvidia,service = "capture-control";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <320>;
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};
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ivccapture@72c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
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nvidia,service = "capture";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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dbg@7c00 {
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compatible = "nvidia,tegra-ivc-cdev";
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nvidia,devname = "camchar-dbg";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <384>;
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};
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dbg@7e00 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <8192>;
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nvidia,ivc-timeout = <50>;
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nvidia,test-timeout = <5000>;
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};
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};
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#if TEGRA_AUDIO_BUS_DT_VERSION >= DT_VERSION_2
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aconnect@2a41000 {
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#endif
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tegra_ape: rtcpu@2993000 {
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compatible = "nvidia,tegra186-ape-ivc";
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status = "disabled";
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#if TEGRA_POWER_DOMAIN_DT_VERSION <= DT_VERSION_1
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power-domains = <&ape_pd>;
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#endif
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reg = <0 0x02993000 0 0x1000>, /* APE EVP */
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<0 0x02990000 0 0x0800>, /* AMISC */
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<0 0x02994000 0 0x2000>; /* ACAST */
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reg-names = "ape-evp", "ape-amisc", "ast-cpu";
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iommus = <&smmu TEGRA_SID_APE_CAM>;
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iommu-group-id = <TEGRA_IOMMU_GROUP_RTCPU>;
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clocks =
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<&tegra_car TEGRA186_CLK_APE>,
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<&tegra_car TEGRA186_CLK_APB2APE>,
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<&tegra_car TEGRA186_CLK_ADSPNEON>,
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<&tegra_car TEGRA186_CLK_ADSP>;
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clock-names =
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"ape",
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"apb2ape",
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"adspneon",
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"adsp";
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resets =
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<&tegra_car TEGRA186_RESET_ADSP_ALL>;
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reset-names =
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"adsp-all";
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interrupt-parent = <&tegra_agic>;
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interrupts =
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AGIC_ROUTE_SPI(INT_WFI, TO_HOST_INTF0),
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AGIC_ROUTE_SPI(INT_WFE, TO_HOST_INTF0),
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/* This is ATKE WDT remote interrupt */
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AGIC_ROUTE_SPI(INT_ATKE_WDT_ERR, TO_HOST_INTF0),
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/* Nameless interrupts below are routed to ADSP */
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AGIC_ROUTE_SPI(INT_ADMA_EOT31, TO_ADSP),
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AGIC_ROUTE_SPI(INT_AHSP_SHRD0, TO_ADSP),
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AGIC_ROUTE_SPI(INT_LIC_TO_APE0, TO_ADSP),
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AGIC_ROUTE_SPI(INT_LIC_TO_APE1, TO_ADSP),
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AGIC_ROUTE_SPI(INT_VI_NOTIFY_LOW, TO_ADSP),
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AGIC_ROUTE_SPI(INT_VI_NOTIFY_HIGH, TO_ADSP),
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AGIC_ROUTE_SPI(INT_I2C_IRQ1, TO_ADSP),
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AGIC_ROUTE_SPI(INT_I2C_IRQ3, TO_ADSP),
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AGIC_ROUTE_SPI(INT_I2C_IRQ8, TO_ADSP),
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AGIC_ROUTE_SPI(INT_SHSP2APE_DB, TO_ADSP),
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AGIC_ROUTE_SPI(INT_ATKE_TMR0, TO_ADSP),
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AGIC_ROUTE_SPI(INT_ATKE_TMR1, TO_ADSP),
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AGIC_ROUTE_SPI(INT_ATKE_TMR2, TO_ADSP),
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AGIC_ROUTE_SPI(INT_ATKE_WDT_IRQ, TO_ADSP),
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AGIC_ROUTE_SPI(INT_ATKE_WDT_FIQ, TO_ADSP);
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interrupt-names = "adsp-wfi", "adsp-wfe", "wdt-remote";
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nvidia,trace = <&tegra_rtcpu_ape_trace 4 0x40200000 0x80000>;
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nvidia,ivc-channels = <&tegra_ape_ivc 2 0x40000000 0x10000>;
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nvidia,autosuspend-delay-ms = <5000>;
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hsp {
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compatible = "nvidia,tegra186-hsp-mailbox";
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#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
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device = <&ape_hsp>;
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#endif
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nvidia,hsp-shared-mailbox = <&ape_hsp 1 &ape_hsp 6>;
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nvidia,hsp-shared-mailbox-names = "ivc-pair", "cmd-pair";
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};
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};
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#if TEGRA_AUDIO_BUS_DT_VERSION >= DT_VERSION_2
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};
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#endif
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tegra_rtcpu_ape_trace: tegra-rtcpu-ape-trace {
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nvidia,enable-printk;
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nvidia,interval-ms = <50>;
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nvidia,log-prefix = "[APE]";
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};
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tegra_ape_ivc: ape-ivc-channels {
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echo@0 {
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compatible = "nvidia,tegra-ivc-cdev";
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nvidia,devname = "camchar-echo";
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nvidia,service = "echo";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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vinotify@12c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-vinotify";
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nvidia,service = "vinotify";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <64>;
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nvidia,frame-size = <128>;
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device = <&tegra_vi>;
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};
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ivccontrol@52c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
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nvidia,service = "capture-control";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <320>;
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};
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ivccapture@72c0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
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nvidia,service = "capture";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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dbg@7c00 {
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compatible = "nvidia,tegra-ivc-cdev";
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nvidia,devname = "camchar-dbg";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <384>;
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};
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dbg@7e00 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <8192>;
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nvidia,ivc-timeout = <50>;
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nvidia,test-timeout = <5000>;
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};
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};
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};
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