forked from rrcarlosr/Jetpack
347 lines
8.1 KiB
C
347 lines
8.1 KiB
C
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/*
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* platform/tegra/fiq_debugger.c
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*
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* Serial Debugger Interface for Tegra
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*
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* Copyright (C) 2008 Google, Inc.
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdarg.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/serial_reg.h>
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#include <linux/slab.h>
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#include <linux/stacktrace.h>
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#include <linux/irqchip/tegra.h>
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#include <linux/tegra_fiq_debugger.h>
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#include <linux/fiq_debugger.h>
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#include <linux/uaccess.h>
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struct tegra_fiq_debugger {
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struct fiq_debugger_pdata pdata;
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void __iomem *debug_port_base;
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bool break_seen;
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};
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/* Legacy UART start */
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static inline void tegra_write(struct tegra_fiq_debugger *t,
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unsigned int val, unsigned int off)
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{
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__raw_writeb(val, t->debug_port_base + off * 4);
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}
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static inline unsigned int tegra_read(struct tegra_fiq_debugger *t,
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unsigned int off)
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{
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return __raw_readb(t->debug_port_base + off * 4);
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}
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static inline unsigned int tegra_read_lsr(struct tegra_fiq_debugger *t)
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{
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unsigned int lsr;
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lsr = tegra_read(t, UART_LSR);
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if (lsr & UART_LSR_BI)
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t->break_seen = true;
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return lsr;
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}
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static int debug_port_init(struct platform_device *pdev)
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{
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struct tegra_fiq_debugger *t;
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t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
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if (tegra_read(t, UART_LSR) & UART_LSR_DR)
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(void)tegra_read(t, UART_RX);
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/* enable rx and lsr interrupt */
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tegra_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
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/* interrupt on every character */
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tegra_write(t, 0, UART_IIR);
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return 0;
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}
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static int debug_getc(struct platform_device *pdev)
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{
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unsigned int lsr;
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struct tegra_fiq_debugger *t;
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t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
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lsr = tegra_read_lsr(t);
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if (lsr & UART_LSR_BI || t->break_seen) {
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t->break_seen = false;
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return FIQ_DEBUGGER_BREAK;
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}
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if (lsr & UART_LSR_DR)
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return tegra_read(t, UART_RX);
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return FIQ_DEBUGGER_NO_CHAR;
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}
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static void debug_putc(struct platform_device *pdev, unsigned int c)
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{
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struct tegra_fiq_debugger *t;
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t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
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while (!(tegra_read_lsr(t) & UART_LSR_THRE))
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cpu_relax();
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tegra_write(t, c, UART_TX);
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}
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static void debug_flush(struct platform_device *pdev)
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{
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struct tegra_fiq_debugger *t;
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t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
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while (!(tegra_read_lsr(t) & UART_LSR_TEMT))
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cpu_relax();
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}
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static void fiq_enable(struct platform_device *pdev, unsigned int irq, bool on)
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{
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#ifdef CONFIG_ARM
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if (on)
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tegra_fiq_enable(irq);
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else
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tegra_fiq_disable(irq);
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#else
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; // do nothing
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#endif
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}
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/* Legacy UART end */
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/* Combined UART start */
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#define CONSOLE_NUM_BYTES_SHIFT 24
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#define CONSOLE_FLUSH_DATA_TO_PORT (1 << 26)
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#define CONSOLE_RING_DOORBELL (1 << 31)
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#define CONSOLE_IS_BUSY (1 << 31)
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#define CONSOLE_WRITE (CONSOLE_RING_DOORBELL | \
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CONSOLE_FLUSH_DATA_TO_PORT)
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static int combined_debug_getc(struct platform_device *pdev)
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{
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return FIQ_DEBUGGER_NO_CHAR;
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}
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static void combined_debug_putc(struct platform_device *pdev, unsigned int c)
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{
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struct tegra_fiq_debugger *t;
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unsigned int val;
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t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
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while (__raw_readl(t->debug_port_base) & CONSOLE_IS_BUSY);
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val = c;
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val |= (CONSOLE_WRITE | (1 << CONSOLE_NUM_BYTES_SHIFT));
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__raw_writel(val, t->debug_port_base);
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}
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static void combined_fiq_enable(struct platform_device *pdev,
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unsigned int irq, bool on)
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{
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#ifdef CONFIG_ARM
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if (on)
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tegra_fiq_enable(irq);
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else
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tegra_fiq_disable(irq);
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#else
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; // do nothing
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#endif
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}
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/* Combined UART end */
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static int tegra_fiq_debugger_id;
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static bool tegra_fiq_combined_uart;
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static void __tegra_serial_debug_init(unsigned int base, int fiq, int irq,
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struct clk *clk, int signal_irq, int wakeup_irq)
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{
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struct tegra_fiq_debugger *t;
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struct platform_device *pdev;
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struct resource *res;
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int res_count;
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t = kzalloc(sizeof(struct tegra_fiq_debugger), GFP_KERNEL);
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if (!t)
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return;
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if (tegra_fiq_combined_uart) {
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t->pdata.uart_init = NULL;
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t->pdata.uart_getc = combined_debug_getc;
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t->pdata.uart_putc = combined_debug_putc;
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t->pdata.uart_flush = NULL;
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t->pdata.fiq_enable = combined_fiq_enable;
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} else {
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t->pdata.uart_init = debug_port_init;
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t->pdata.uart_getc = debug_getc;
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t->pdata.uart_putc = debug_putc;
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t->pdata.uart_flush = debug_flush;
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t->pdata.fiq_enable = fiq_enable;
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}
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t->debug_port_base = ioremap(base, PAGE_SIZE);
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if (!t->debug_port_base) {
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pr_err("Failed to ioremap for fiq debugger\n");
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goto out1;
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}
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res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
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if (!res)
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goto out2;
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pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
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if (!pdev)
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goto out3;
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if (fiq >= 0) {
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res[0].flags = IORESOURCE_IRQ;
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res[0].start = fiq;
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res[0].end = fiq;
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res[0].name = "fiq";
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} else {
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res[0].flags = IORESOURCE_IRQ;
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res[0].start = irq;
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res[0].end = irq;
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res[0].name = "uart_irq";
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}
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res[1].flags = IORESOURCE_IRQ;
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res[1].start = signal_irq;
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res[1].end = signal_irq;
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res[1].name = "signal";
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res_count = 2;
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if (wakeup_irq >= 0) {
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res[2].flags = IORESOURCE_IRQ;
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res[2].start = wakeup_irq;
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res[2].end = wakeup_irq;
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res[2].name = "wakeup";
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res_count++;
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}
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pdev->name = "fiq_debugger";
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pdev->id = tegra_fiq_debugger_id++;
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pdev->dev.platform_data = &t->pdata;
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pdev->resource = res;
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pdev->num_resources = res_count;
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if (platform_device_register(pdev)) {
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pr_err("Failed to register fiq debugger\n");
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goto out4;
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}
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return;
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out4:
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kfree(pdev);
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out3:
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kfree(res);
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out2:
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iounmap(t->debug_port_base);
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out1:
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kfree(t);
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}
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void tegra_serial_debug_init(unsigned int base, int fiq,
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struct clk *clk, int signal_irq, int wakeup_irq)
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{
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__tegra_serial_debug_init(base, fiq, -1, clk, signal_irq, wakeup_irq);
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}
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void tegra_serial_debug_init_irq_mode(unsigned int base, int irq,
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struct clk *clk, int signal_irq, int wakeup_irq)
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{
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__tegra_serial_debug_init(base, -1, irq, clk, signal_irq, wakeup_irq);
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}
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static int __init tegra_fiq_debugger_init(void)
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{
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struct device_node *dn, *dn_debugger;
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struct resource resource;
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unsigned int uartbase = 0;
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int irq = -1;
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dn_debugger = of_find_compatible_node(NULL, NULL,
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"nvidia,fiq-debugger");
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if (!dn_debugger) {
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pr_err("%s: no fiq_debugger node\n", __func__);
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return -ENODEV;
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}
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/* Search for the IO memory of console port */
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if (of_property_read_bool(dn_debugger, "use-console-port")) {
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dn = of_find_node_with_property(NULL, "console-port");
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if (!dn) {
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pr_err("%s: no console-port found\n", __func__);
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return -ENODEV;
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}
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} else
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dn = dn_debugger;
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if (of_find_node_with_property(NULL, "combined-uart")) {
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tegra_fiq_combined_uart = true;
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if (of_address_to_resource(dn, 1, &resource)) {
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pr_err("%s: could not get IO memory\n", __func__);
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return -ENXIO;
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}
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} else {
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tegra_fiq_combined_uart = false;
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if (of_address_to_resource(dn, 0, &resource)) {
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pr_err("%s: could not get IO memory\n", __func__);
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return -ENXIO;
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}
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}
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uartbase = resource.start;
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pr_debug("%s: found console port at %08X\n", __func__, uartbase);
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/* Search for the interrupt which acts as trigger of FIQ debugger */
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if (of_property_read_bool(dn_debugger, "use-wdt-irq")) {
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dn = of_find_compatible_node(NULL, NULL, "nvidia,tegra-wdt");
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if (!dn) {
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pr_err("%s: no tegra-wdt found\n", __func__);
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return -ENODEV;
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}
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} else
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dn = dn_debugger;
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irq = irq_of_parse_and_map(dn, 0);
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if (irq <= 0) {
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pr_err("%s: could not find interrupt for FIQ\n", __func__);
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return -ENODEV;
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}
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pr_info("%s: found FIQ source (IRQ %d)\n", __func__, irq);
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tegra_serial_debug_init(uartbase, irq, NULL, -1, -1);
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return 0;
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}
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subsys_initcall(tegra_fiq_debugger_init)
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