forked from rrcarlosr/Jetpack
104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
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/*
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __SOC_TEGRA_FUSE_H__
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#define __SOC_TEGRA_FUSE_H__
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#include <linux/tegra-soc.h>
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#define TEGRA_FUSE_PRODUCTION_MODE 0x0
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#define FUSE_FUSEBYPASS_0 0x24
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#define FUSE_WRITE_ACCESS_SW_0 0x30
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#define FUSE_SKU_INFO 0x10
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#define FUSE_SKU_MSB_MASK 0xFF00
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#define FUSE_SKU_MSB_SHIFT 8
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#define FUSE_OPT_FT_REV_0 0x28
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#define FUSE_SKU_USB_CALIB_0 0xf0
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#define TEGRA_FUSE_SKU_CALIB_0 0xf0
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#define FUSE_OPT_VENDOR_CODE 0x100
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#define FUSE_OPT_VENDOR_CODE_MASK 0xf
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#define FUSE_OPT_FAB_CODE 0x104
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#define FUSE_OPT_FAB_CODE_MASK 0x3f
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#define FUSE_OPT_LOT_CODE_0 0x108
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#define FUSE_OPT_LOT_CODE_1 0x10c
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#define FUSE_OPT_WAFER_ID 0x118
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#define FUSE_OPT_WAFER_ID_MASK 0x3f
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#define FUSE_OPT_X_COORDINATE 0x114
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#define FUSE_OPT_X_COORDINATE_MASK 0x1ff
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#define FUSE_OPT_Y_COORDINATE 0x118
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#define FUSE_OPT_Y_COORDINATE_MASK 0x1ff
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#define TEGRA30_FUSE_SATA_CALIB 0x124
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#define FUSE_OPT_SUBREVISION 0x148
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#define FUSE_OPT_SUBREVISION_MASK 0xF
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#define FUSE_GCPLEX_CONFIG_FUSE_0 0x1c8
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#define FUSE_TDIODE_CALIB 0x274
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#define FUSE_RESERVED_CALIB0_0 0x204
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#define FUSE_OPT_GPU_TPC0_DISABLE_0 0x20c
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#define FUSE_OPT_GPU_TPC1_DISABLE_0 0x23c
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#define FUSE_USB_CALIB_EXT_0 0x250
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#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
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#define FUSE_CP_REV 0x90
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#define TEGRA_FUSE_CP_REV_0_3 (3)
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#define FUSE_IP_DISABLE_0 0x4b0
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#define FUSE_IP_DISABLE_0_NVLINK_MASK 0x10
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#define FUSE_UCODE_MINION_REV_0 0x4d4
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#define FUSE_UCODE_MINION_REV_0_MASK 0x7
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#define FUSE_SECURE_MINION_DEBUG_DIS_0 0x4d8
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#define FUSE_SECURE_MINION_DEBUG_DIS_0_MASK 0x1
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#ifndef __ASSEMBLY__
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u32 tegra_read_chipid(void);
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u32 tegra_read_straps(void);
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u32 tegra_read_ram_code(void);
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u32 tegra_read_chipid(void);
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enum tegra_chipid tegra_get_chipid(void);
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int tegra_fuse_control_read(unsigned long offset, u32 *value);
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void tegra_fuse_control_write(u32 value, unsigned long offset);
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int tegra_fuse_readl(unsigned long offset, u32 *value);
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void tegra_fuse_writel(u32 val, unsigned long offset);
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enum tegra_revision tegra_chip_get_revision(void);
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int tegra_fuse_clock_enable(void);
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int tegra_fuse_clock_disable(void);
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u32 tegra_get_sku_id(void);
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/* TODO: Dummy implementation till upstream fuse driver implements these*/
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static inline bool tegra_spare_fuse(int bit)
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{ return 0; }
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static inline int tegra_get_sku_override(void)
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{ return 0; }
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#endif /* __ASSEMBLY__ */
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u32 tegra_fuse_get_subrevision(void);
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#endif /* __SOC_TEGRA_FUSE_H__ */
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