forked from rrcarlosr/Jetpack
42 lines
1.6 KiB
Plaintext
42 lines
1.6 KiB
Plaintext
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NDS32 is a new high-performance 32-bit RISC microprocessor core.
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http://www.andestech.com/
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AndeStar ISA
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============
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AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
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achieve optimal system performance, code density, and power efficiency.
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It contains the following features:
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- Intermixable 32-bit and 16-bit instruction sets without the need for
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mode switch.
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- 16-bit instructions as a frequently used subset of 32-bit instructions.
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- RISC-style register-based instruction set.
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- 32 32-bit General Purpose Registers (GPR).
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- Upto 1024 User Special Registers (USR) for existing and extension
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instructions.
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- Rich load/store instructions for...
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- Single memory access with base address update.
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- Multiple aligned and unaligned memory accesses for memory copy and stack
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operations.
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- Data prefetch to improve data cache performance.
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- Non-bus locking synchronization instructions.
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- PC relative jump and PC read instructions for efficient position independent
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code.
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- Multiply-add and multiple-sub with 64-bit accumulator.
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- Instruction for efficient power management.
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- Bi-endian support.
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- Three instruction extension space for application acceleration:
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- Performance extension.
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- Andes future extensions (for floating-point, multimedia, etc.)
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- Customer extensions.
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AndesCore CPU
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=============
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Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
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For details about N12 CPU family, please check doc/README.N1213.
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The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
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other associated software are actively supported by Andes Technology Corporation.
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