forked from rrcarlosr/Jetpack
71 lines
2.4 KiB
Plaintext
71 lines
2.4 KiB
Plaintext
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#
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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if VENDOR_INTEL
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choice
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prompt "Mainboard model"
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optional
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config TARGET_BAYLEYBAY
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bool "Bayley Bay"
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help
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This is the Intel Bayley Bay Customer Reference Board. It contains an
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Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
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4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
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PCIe and some other sensor interfaces.
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config TARGET_COUGARCANYON2
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bool "Cougar Canyon 2"
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help
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This is the Intel Cougar Canyon 2 Customer Reference Board. It
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is built on the Chief River platform with Intel Ivybridge Processor
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and Panther Point chipset. The board has 4GB RAM, with some other
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peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
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config TARGET_CROWNBAY
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bool "Crown Bay"
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help
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This is the Intel Crown Bay Customer Reference Board. It contains
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the Intel Atom Processor E6xx populated on the COM Express module
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with 1GB DDR2 soldered down memory and a carrier board with the
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Intel Platform Controller Hub EG20T, other system components and
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peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
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config TARGET_GALILEO
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bool "Galileo"
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help
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This is the Intel Galileo board, which is the first in a family of
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Arduino-certified development and prototyping boards based on Intel
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architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
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single-core, single-thread, Intel Pentium processor instrunction set
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architecture (ISA) compatible, operating at speeds up to 400Mhz,
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along with 256MB DDR3 memory. It supports a wide range of industry
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standard I/O interfaces, including a full-sized mini-PCIe slot,
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one 100Mb Ethernet port, a microSD card slot, a USB host port and
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a USB client port.
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config TARGET_MINNOWMAX
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bool "Minnowboard MAX"
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help
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This is the Intel Minnowboard MAX. It contains an Atom E3800
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processor in a small form factor with Ethernet, micro-SD, USB 2,
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USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
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It requires some binary blobs - see README.x86 for details.
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Note that PCIE_ECAM_BASE is set up by the FSP so the value used
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by U-Boot matches that value.
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endchoice
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source "board/intel/bayleybay/Kconfig"
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source "board/intel/cougarcanyon2/Kconfig"
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source "board/intel/crownbay/Kconfig"
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source "board/intel/galileo/Kconfig"
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source "board/intel/minnowmax/Kconfig"
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endif
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