forked from rrcarlosr/Jetpack
87 lines
1.9 KiB
C
87 lines
1.9 KiB
C
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{2, 2140, 0, 4, 4, 0x0, 0x0},
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{1, 2140, 0, 4, 4, 0x0, 0x0},
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{}
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};
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/* DP-DDR DIMM */
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static const struct board_specific_parameters udimm2[] = {
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/*
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* memory controller 2
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{2, 2140, 0, 4, 4, 0x0, 0x0},
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{1, 2140, 0, 4, 4, 0x0, 0x0},
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{}
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};
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static const struct board_specific_parameters rdimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{4, 2140, 0, 5, 4, 0x0, 0x0},
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{2, 2140, 0, 5, 4, 0x0, 0x0},
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{1, 2140, 0, 4, 4, 0x0, 0x0},
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{}
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};
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/* DP-DDR DIMM */
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static const struct board_specific_parameters rdimm2[] = {
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/*
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* memory controller 2
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3
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*/
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{4, 2140, 0, 5, 4, 0x0, 0x0},
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{2, 2140, 0, 5, 4, 0x0, 0x0},
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{1, 2140, 0, 4, 4, 0x0, 0x0},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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udimm0,
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udimm2,
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};
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static const struct board_specific_parameters *rdimms[] = {
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rdimm0,
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rdimm0,
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rdimm2,
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};
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#endif
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