forked from rrcarlosr/Jetpack
112 lines
2.7 KiB
C
112 lines
2.7 KiB
C
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/*
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* include/configs/alt.h
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* This file is alt board configuration.
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ALT_H
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#define __ALT_H
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#undef DEBUG
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#define CONFIG_R8A7794
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#define CONFIG_RMOBILE_BOARD_STRING "Alt"
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#include "rcar-gen2-common.h"
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#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
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#define CONFIG_SYS_TEXT_BASE 0x70000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0xE6304000
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#endif
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#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
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#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
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#else
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#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
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#endif
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#define STACK_AREA_SIZE 0xC000
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#define LOW_LEVEL_MERAM_STACK \
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(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
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/* MEMORY */
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#define RCAR_GEN2_SDRAM_BASE 0x40000000
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#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
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#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE
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/* FLASH */
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#define CONFIG_SPI
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#define CONFIG_SH_QSPI
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#define CONFIG_SPI_FLASH_QUAD
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#define CONFIG_SYS_NO_FLASH
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/* SH Ether */
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
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#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
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#define CONFIG_SYS_TMU_CLK_DIV 4
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/* i2c */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SH
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
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#define CONFIG_SYS_I2C_SH_SPEED0 400000
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#define CONFIG_SYS_I2C_SH_SPEED1 400000
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#define CONFIG_SYS_I2C_SH_SPEED2 400000
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#define CONFIG_SH_I2C_DATA_HIGH 4
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#define CONFIG_SH_I2C_DATA_LOW 5
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#define CONFIG_SH_I2C_CLOCK 10000000
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#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
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/* USB */
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_RMOBILE
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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/* MMCIF */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SH_MMCIF
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#define CONFIG_SH_MMCIF_ADDR 0xee200000
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#define CONFIG_SH_MMCIF_CLK 48000000
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/* Module stop status bits */
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/* INTC-RT */
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#define CONFIG_SMSTP0_ENA 0x00400000
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/* MSIF */
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#define CONFIG_SMSTP2_ENA 0x00002000
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/* INTC-SYS, IRQC */
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#define CONFIG_SMSTP4_ENA 0x00000180
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/* SCIF2 */
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#define CONFIG_SMSTP7_ENA 0x00080000
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/* SDHI */
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#define CONFIG_SH_SDHI_FREQ 97500000
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#endif /* __ALT_H */
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