forked from rrcarlosr/Jetpack
169 lines
4.1 KiB
C
169 lines
4.1 KiB
C
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/*
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* NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
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*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Copyright (c) 2008 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_lbc.h>
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#include <nand.h>
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#define WINDOW_SIZE 8192
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static void nand_wait(void)
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{
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fsl_lbc_t *regs = LBC_BASE_ADDR;
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for (;;) {
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uint32_t status = in_be32(®s->ltesr);
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if (status == 1)
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return;
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if (status & 1) {
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puts("read failed (ltesr)\n");
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for (;;);
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}
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}
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}
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#ifdef CONFIG_TPL_BUILD
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int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
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#else
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static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
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#endif
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{
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fsl_lbc_t *regs = LBC_BASE_ADDR;
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uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
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const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
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const int block_shift = large ? 17 : 14;
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const int block_size = 1 << block_shift;
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const int page_size = large ? 2048 : 512;
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const int bad_marker = large ? page_size + 0 : page_size + 5;
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int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
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int pos = 0;
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char *dst = vdst;
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if (offs & (block_size - 1)) {
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puts("bad offset\n");
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for (;;);
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}
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if (large) {
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fmr |= FMR_ECCM;
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out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
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(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
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out_be32(®s->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_CW1 << FIR_OP3_SHIFT) |
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(FIR_OP_RBW << FIR_OP4_SHIFT));
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} else {
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out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
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out_be32(®s->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_RBW << FIR_OP3_SHIFT));
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}
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out_be32(®s->fbcr, 0);
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clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
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while (pos < uboot_size) {
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int i = 0;
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out_be32(®s->fbar, offs >> block_shift);
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do {
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int j;
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unsigned int page_offs = (offs & (block_size - 1)) << 1;
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out_be32(®s->ltesr, ~0);
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out_be32(®s->lteatr, 0);
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out_be32(®s->fpar, page_offs);
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out_be32(®s->fmr, fmr);
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out_be32(®s->lsor, 0);
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nand_wait();
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page_offs %= WINDOW_SIZE;
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/*
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* If either of the first two pages are marked bad,
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* continue to the next block.
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*/
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if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
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puts("skipping\n");
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offs = (offs + block_size) & ~(block_size - 1);
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pos &= ~(block_size - 1);
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break;
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}
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for (j = 0; j < page_size; j++)
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dst[pos + j] = buf[page_offs + j];
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pos += page_size;
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offs += page_size;
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} while ((offs & (block_size - 1)) && (pos < uboot_size));
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}
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return 0;
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}
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/*
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* Defines a static function nand_load_image() here, because non-static makes
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* the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
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*/
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#ifndef CONFIG_TPL_BUILD
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#define nand_spl_load_image(offs, uboot_size, vdst) \
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nand_load_image(offs, uboot_size, vdst)
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#endif
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/*
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* The main entry for NAND booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from NAND into SDRAM and starts it from there.
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*/
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
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CONFIG_SYS_NAND_U_BOOT_SIZE,
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(void *)CONFIG_SYS_NAND_U_BOOT_DST);
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#ifdef CONFIG_NAND_ENV_DST
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST);
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#ifdef CONFIG_ENV_OFFSET_REDUND
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nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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#endif
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#endif
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#ifdef CONFIG_SPL_FLUSH_IMAGE
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/*
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* Clean d-cache and invalidate i-cache, to
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* make sure that no stale data is executed.
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*/
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flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
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#endif
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puts("transfering control\n");
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/*
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* Jump to U-Boot image
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*/
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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(*uboot)();
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}
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