forked from rrcarlosr/Jetpack
60 lines
1.8 KiB
ArmAsm
60 lines
1.8 KiB
ArmAsm
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/*
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* (C) Copyright 2008
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* based on board/amcc/yosemite/init.S
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* original Copyright not specified there
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <ppc_asm.tmpl>
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#include <config.h>
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#include <asm/mmu.h>
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
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* the speed up boot process. It is patched after relocation to enable SA_I
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*/
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tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
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0, AC_RWX | SA_G/*|SA_I*/)
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
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0, AC_RWX | SA_G )
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tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
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0, AC_RWX | SA_IG )
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tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
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0, AC_RW | SA_IG )
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/* PCI */
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tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
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0, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
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0, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
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0, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
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0, AC_RW | SA_IG )
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tlbtab_end
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