forked from rrcarlosr/Jetpack
94 lines
1.5 KiB
C
94 lines
1.5 KiB
C
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/*
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* Copyright 2007 Freescale Semiconductor.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __BCSR_H_
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#define __BCSR_H_
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#include <common.h>
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/* BCSR Bit definitions
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* BCSR 0 *
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0:3 ccb sys pll
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4:6 cfg core pll
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7 cfg boot seq
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* BCSR 1 *
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0:2 cfg rom lock
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3:5 cfg host agent
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6 PCI IO
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7 cfg RIO size
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* BCSR 2 *
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0:4 QE PLL
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5 QE clock
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6 cfg PCI arbiter
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* BCSR 3 *
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0 TSEC1 reduce
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1 TSEC2 reduce
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2:3 TSEC1 protocol
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4:5 TSEC2 protocol
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6 PHY1 slave
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7 PHY2 slave
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* BCSR 4 *
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4 clock enable
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5 boot EPROM
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6 GETH transactive reset
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7 BRD write potect
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* BCSR 5 *
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1:3 Leds 1-3
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4 UPC1 enable
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5 UPC2 enable
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6 UPC2 pos
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7 RS232 enable
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* BCSR 6 *
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0 CFG ver 0
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1 CFG ver 1
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6 Register config led
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7 Power on reset
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* BCSR 7 *
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2 board host mode indication
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5 enable TSEC1 PHY
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6 enable TSEC2 PHY
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* BCSR 8 *
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0 UCC GETH1 enable
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1 UCC GMII enable
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3 UCC TBI enable
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5 UCC MII enable
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7 Real time clock reset
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* BCSR 9 *
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0 UCC2 GETH enable
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1 UCC2 GMII enable
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3 UCC2 TBI enable
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5 UCC2 MII enable
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6 Ready only - indicate flash ready after burning
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7 Flash write protect
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*/
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#define BCSR_UCC1_GETH_EN (0x1 << 7)
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#define BCSR_UCC2_GETH_EN (0x1 << 7)
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#define BCSR_UCC1_MODE_MSK (0x3 << 4)
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#define BCSR_UCC2_MODE_MSK (0x3 << 0)
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/*BCSR Utils functions*/
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void enable_8568mds_duart(void);
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void enable_8568mds_flash_write(void);
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void disable_8568mds_flash_write(void);
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void enable_8568mds_qe_mdio(void);
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#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
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void reset_8568mds_uccs(void);
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#endif
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#endif /* __BCSR_H_ */
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