forked from rrcarlosr/Jetpack
441 lines
14 KiB
C
441 lines
14 KiB
C
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/*
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* This is the main board level file for the Redwood AMCC board.
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*
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* (C) Copyright 2008
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* Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "redwood.h"
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <asm/io.h>
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int compare_to_true(char *str);
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char *remove_l_w_space(char *in_str);
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char *remove_t_w_space(char *in_str);
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int get_console_port(void);
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static void early_init_EBC(void);
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static int bootdevice_selected(void);
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static void early_reinit_EBC(int);
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static void early_init_UIC(void);
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/*
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* Define Boot devices
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*/
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#define BOOT_FROM_8BIT_SRAM 0x00
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#define BOOT_FROM_16BIT_SRAM 0x01
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#define BOOT_FROM_32BIT_SRAM 0x02
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#define BOOT_FROM_8BIT_NAND 0x03
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#define BOOT_FROM_16BIT_NOR 0x04
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#define BOOT_DEVICE_UNKNOWN 0xff
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/*
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* EBC Devices Characteristics
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* Peripheral Bank Access Parameters - EBC_BxAP
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* Peripheral Bank Configuration Register - EBC_BxCR
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*/
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/*
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* 8 bit width SRAM
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* BU Value
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* BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
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* B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
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* B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
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*/
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#define EBC_BXAP_8BIT_SRAM \
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED
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#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
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#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
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/*
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* NAND flash
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* BU Value
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* BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
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* B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
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* B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
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*/
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#define EBC_BXAP_NAND \
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED
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/*
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* NOR flash
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* BU Value
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* BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
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* B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
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* B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
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*/
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#define EBC_BXAP_NOR \
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
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EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED
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/*
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* FPGA
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* BU value :
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* B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
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* B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
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*/
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#define EBC_BXAP_FPGA \
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \
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EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \
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EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \
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EBC_BXAP_PEN_DISABLED
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#define EBC_BXCR_8BIT_SRAM_CS0 \
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EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
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#define EBC_BXCR_32BIT_SRAM_CS0 \
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EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
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#define EBC_BXCR_NAND_CS0 \
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EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
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#define EBC_BXCR_16BIT_SRAM_CS0 \
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EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
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#define EBC_BXCR_NOR_CS0 \
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EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
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#define EBC_BXCR_NOR_CS1 \
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EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
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#define EBC_BXCR_NAND_CS1 \
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EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
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#define EBC_BXCR_NAND_CS2 \
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EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
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#define EBC_BXCR_SRAM_CS2 \
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EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
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#define EBC_BXCR_LARGE_FLASH_CS2 \
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EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
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#define EBC_BXCR_FPGA_CS3 \
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EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
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/*****************************************************************************
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* UBOOT initiated board specific function calls
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****************************************************************************/
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int board_early_init_f(void)
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{
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int computed_boot_device = BOOT_DEVICE_UNKNOWN;
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/*
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* Initialise EBC
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*/
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early_init_EBC();
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/*
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* Determine which boot device was selected
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*/
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computed_boot_device = bootdevice_selected();
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/*
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* Reinit EBC based on selected boot device
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*/
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early_reinit_EBC(computed_boot_device);
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/*
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* Setup for UIC on 460SX redwood board
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*/
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early_init_UIC();
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: Redwood - AMCC 460SX Reference Board");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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static void early_init_EBC(void)
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{
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/*
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* Initialize EBC CONFIG -
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* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
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* default value :
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* 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
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*/
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mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_ENABLE |
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EBC_CFG_RTC_16PERCLK |
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EBC_CFG_ATC_PREVIOUS |
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EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS |
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EBC_CFG_OEO_PREVIOUS |
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EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
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/*
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* PART 1 : Initialize EBC Bank 3
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* ==============================
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* Bank1 is always associated to the EPLD.
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* It has to be initialized prior to other banks settings computation
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* since some board registers values may be needed to determine the
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* boot type
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*/
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mtebc(PB1AP, EBC_BXAP_FPGA);
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mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
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}
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static int bootdevice_selected(void)
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{
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unsigned long sdr0_pinstp;
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unsigned long bootstrap_settings;
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int computed_boot_device = BOOT_DEVICE_UNKNOWN;
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/*
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* Determine which boot device was selected
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* =================================================
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*
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* Read Pin Strap Register in PPC460SX
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* Result can either be :
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* - Boot strap = boot from EBC 8bits => Small Flash
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* - Boot strap = boot from PCI
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* - Boot strap = IIC
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* In case of boot from IIC, read Serial Device Strap Register1
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*
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* Result can either be :
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* - Boot from EBC - EBC Bus Width = 8bits => Small Flash
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* - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
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* - Boot from PCI
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*/
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/* Read Pin Strap Register in PPC460SX */
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mfsdr(SDR0_PINSTP, sdr0_pinstp);
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bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
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switch (bootstrap_settings) {
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case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
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/*
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* Boot from SRAM, 8bit width
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*/
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computed_boot_device = BOOT_FROM_8BIT_SRAM;
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break;
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case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
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/*
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* Boot from SRAM, 32bit width
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*/
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computed_boot_device = BOOT_FROM_32BIT_SRAM;
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break;
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case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
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/*
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* Boot from NAND, 8bit width
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*/
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computed_boot_device = BOOT_FROM_8BIT_NAND;
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break;
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case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
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/*
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* Boot from SRAM, 16bit width
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* Boot setting in IIC EEPROM 0x50
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*/
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computed_boot_device = BOOT_FROM_16BIT_SRAM;
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break;
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case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
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/*
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* Boot from NOR, 16bit width
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* Boot setting in IIC EEPROM 0x54
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*/
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computed_boot_device = BOOT_FROM_16BIT_NOR;
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break;
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default:
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/* should not be */
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computed_boot_device = BOOT_DEVICE_UNKNOWN;
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break;
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}
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return computed_boot_device;
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}
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static void early_reinit_EBC(int computed_boot_device)
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{
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/*
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* Compute EBC settings depending on selected boot device
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* ======================================================
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*
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* Resulting EBC init will be among following configurations :
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*
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* - Boot from EBC 8bits => boot from Small Flash selected
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* EBC-CS0 = Small Flash
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* EBC-CS2 = Large Flash and SRAM
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*
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* - Boot from EBC 16bits => boot from Large Flash or SRAM
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* EBC-CS0 = Large Flash or SRAM
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* EBC-CS2 = Small Flash
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*
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* - Boot from PCI
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* EBC-CS0 = not initialized to avoid address contention
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* EBC-CS2 = same as boot from Small Flash selected
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*/
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unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
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unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
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unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
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switch (computed_boot_device) {
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/*-------------------------------------------------------------------*/
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case BOOT_FROM_8BIT_SRAM:
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/*-------------------------------------------------------------------*/
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ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
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ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
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ebc0_cs1_bxap_value = EBC_BXAP_NOR;
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ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
|
||
|
|
ebc0_cs2_bxap_value = EBC_BXAP_NAND;
|
||
|
|
ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
case BOOT_FROM_16BIT_SRAM:
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
|
||
|
|
ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
|
||
|
|
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
|
||
|
|
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
|
||
|
|
ebc0_cs2_bxap_value = EBC_BXAP_NAND;
|
||
|
|
ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
case BOOT_FROM_32BIT_SRAM:
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
|
||
|
|
ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
|
||
|
|
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
|
||
|
|
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
|
||
|
|
ebc0_cs2_bxap_value = EBC_BXAP_NAND;
|
||
|
|
ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
case BOOT_FROM_16BIT_NOR:
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
ebc0_cs0_bxap_value = EBC_BXAP_NOR;
|
||
|
|
ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
|
||
|
|
ebc0_cs1_bxap_value = EBC_BXAP_NAND;
|
||
|
|
ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
|
||
|
|
ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
|
||
|
|
ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
case BOOT_FROM_8BIT_NAND:
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
ebc0_cs0_bxap_value = EBC_BXAP_NAND;
|
||
|
|
ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
|
||
|
|
ebc0_cs1_bxap_value = EBC_BXAP_NOR;
|
||
|
|
ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
|
||
|
|
ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
|
||
|
|
ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
default:
|
||
|
|
/*-------------------------------------------------------------------*/
|
||
|
|
/* BOOT_DEVICE_UNKNOWN */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
mtebc(PB0AP, ebc0_cs0_bxap_value);
|
||
|
|
mtebc(PB0CR, ebc0_cs0_bxcr_value);
|
||
|
|
mtebc(PB1AP, ebc0_cs1_bxap_value);
|
||
|
|
mtebc(PB1CR, ebc0_cs1_bxcr_value);
|
||
|
|
mtebc(PB2AP, ebc0_cs2_bxap_value);
|
||
|
|
mtebc(PB2CR, ebc0_cs2_bxcr_value);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void early_init_UIC(void)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Initialise UIC registers. Clear all interrupts. Disable all
|
||
|
|
* interrupts.
|
||
|
|
* Set critical interrupt values. Set interrupt polarities. Set
|
||
|
|
* interrupt trigger levels. Make bit 0 High priority. Clear all
|
||
|
|
* interrupts again.
|
||
|
|
*/
|
||
|
|
mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
|
||
|
|
mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
|
||
|
|
mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
|
||
|
|
* interrupts */
|
||
|
|
mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
|
||
|
|
mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
|
||
|
|
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
|
||
|
|
mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
|
||
|
|
|
||
|
|
mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
|
||
|
|
mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
|
||
|
|
mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
|
||
|
|
* interrupts */
|
||
|
|
mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
|
||
|
|
mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
|
||
|
|
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
|
||
|
|
mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
|
||
|
|
|
||
|
|
mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
|
||
|
|
mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
|
||
|
|
mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
|
||
|
|
* interrupts */
|
||
|
|
mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
|
||
|
|
mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
|
||
|
|
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
|
||
|
|
mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
|
||
|
|
|
||
|
|
mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
|
||
|
|
mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
|
||
|
|
* cascade to be checked */
|
||
|
|
mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
|
||
|
|
* interrupts */
|
||
|
|
mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
|
||
|
|
mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
|
||
|
|
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
|
||
|
|
mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
|
||
|
|
|
||
|
|
}
|