forked from rrcarlosr/Jetpack
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Definitions for Jetson tegra210-jetson-tx1-p2597-2180-a01-devkit
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* board.
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*
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* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#define JETSON_COMPATIBLE "nvidia,p2597-0000+p2180-1000"
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/* SoC function name for clock signal on 40-pin header pin 7 */
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#define HDR40_CLK "aud"
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/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
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#define HDR40_I2S "i2s1"
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/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
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#define HDR40_SPI "spi1"
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/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
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#define HDR40_UART "uarta"
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/* SoC pin name definitions for 40-pin header */
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#define HDR40_PIN7 "aud_mclk_pbb0"
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#define HDR40_PIN11 "uart1_rts_pu2"
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#define HDR40_PIN12 "dap1_sclk_pb3"
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#define HDR40_PIN13 "pe6"
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#define HDR40_PIN16 "dmic3_dat_pe5"
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#define HDR40_PIN18 "modem_wake_ap_px0"
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#define HDR40_PIN19 "spi1_mosi_pc0"
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#define HDR40_PIN21 "spi1_miso_pc1"
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#define HDR40_PIN23 "spi1_sck_pc2"
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#define HDR40_PIN24 "spi1_cs0_pc3"
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#define HDR40_PIN26 "spi1_cs1_pc4"
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#define HDR40_PIN29 "gpio_x1_aud_pbb3"
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#define HDR40_PIN31 "motion_int_px2"
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#define HDR40_PIN32 "dmic3_clk_pe4"
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#define HDR40_PIN33 "ap_wake_nfc_ph7"
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#define HDR40_PIN35 "dap1_fs_pb0"
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#define HDR40_PIN36 "uart1_cts_pu3"
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#define HDR40_PIN37 "als_prox_int_px3"
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#define HDR40_PIN38 "dap1_din_pb1"
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#define HDR40_PIN40 "dap1_dout_pb2"
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