forked from rrcarlosr/Jetpack
40 lines
1.4 KiB
C
40 lines
1.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Definitions for Jetson tegra186-quill-p3310-1000-c03-00-base board.
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*
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* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#define JETSON_COMPATIBLE "nvidia,p2597-0000+p3310-1000"
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/* SoC function name for clock signal on 40-pin header pin 7 */
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#define HDR40_CLK "aud"
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/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
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#define HDR40_I2S "i2s1"
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/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
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#define HDR40_SPI "spi4"
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/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
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#define HDR40_UART "uarta"
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/* SoC pin name definitions for 40-pin header */
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#define HDR40_PIN7 "aud_mclk_pj4"
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#define HDR40_PIN11 "uart1_rts_pt2"
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#define HDR40_PIN12 "dap1_sclk_pj0"
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#define HDR40_PIN13 "gpio_aud0_pj5"
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#define HDR40_PIN16 "can_gpio0_paa0"
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#define HDR40_PIN18 "gpio_mdm2_py1"
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#define HDR40_PIN19 "gpio_cam6_pn5"
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#define HDR40_PIN21 "gpio_cam5_pn4"
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#define HDR40_PIN23 "gpio_cam4_pn3"
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#define HDR40_PIN24 "gpio_cam7_pn6"
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#define HDR40_PIN29 "gpio_aud1_pj6"
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#define HDR40_PIN31 "can_gpio2_paa2"
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#define HDR40_PIN32 "can_gpio1_paa1"
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#define HDR40_PIN33 "gpio_pq5_pi5"
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#define HDR40_PIN35 "dap1_fs_pj3"
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#define HDR40_PIN36 "uart1_cts_pt3"
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#define HDR40_PIN37 "gpio_pq4_pi4"
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#define HDR40_PIN38 "dap1_din_pj2"
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#define HDR40_PIN40 "dap1_dout_pj1"
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