forked from rrcarlosr/Jetpack
167 lines
5.3 KiB
C
167 lines
5.3 KiB
C
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/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_TEGRA_T18X_AGIC_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_TEGRA_T18X_AGIC_H
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define ROUTE_TO_HOST_INTF0 0
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#define ROUTE_TO_HOST_INTF1 1
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#define ROUTE_TO_HOST_INTF2 2
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#define ROUTE_TO_HOST_INTF3 3
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#define ROUTE_TO_ADSP 4
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/* The DT adds an offset of 32 to IRQs defined as SPI */
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#define AGIC_IRQ(x) (x - 32)
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/* LEVEL_HIGH SPI */
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#define AGIC_ROUTE_SPI(x,c) <GIC_SPI x IRQ_TYPE_LEVEL_HIGH ROUTE_##c>
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/* INT_ADMA Channel End of Transfer Interrupt */
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#define INT_ADMA_EOT0 AGIC_IRQ(32)
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#define INT_ADMA_EOT1 AGIC_IRQ(33)
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#define INT_ADMA_EOT2 AGIC_IRQ(34)
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#define INT_ADMA_EOT3 AGIC_IRQ(35)
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#define INT_ADMA_EOT4 AGIC_IRQ(36)
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#define INT_ADMA_EOT5 AGIC_IRQ(37)
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#define INT_ADMA_EOT6 AGIC_IRQ(38)
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#define INT_ADMA_EOT7 AGIC_IRQ(39)
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#define INT_ADMA_EOT8 AGIC_IRQ(40)
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#define INT_ADMA_EOT9 AGIC_IRQ(41)
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#define INT_ADMA_EOT10 AGIC_IRQ(42)
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#define INT_ADMA_EOT11 AGIC_IRQ(43)
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#define INT_ADMA_EOT12 AGIC_IRQ(44)
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#define INT_ADMA_EOT13 AGIC_IRQ(45)
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#define INT_ADMA_EOT14 AGIC_IRQ(46)
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#define INT_ADMA_EOT15 AGIC_IRQ(47)
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#define INT_ADMA_EOT16 AGIC_IRQ(48)
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#define INT_ADMA_EOT17 AGIC_IRQ(49)
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#define INT_ADMA_EOT18 AGIC_IRQ(50)
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#define INT_ADMA_EOT19 AGIC_IRQ(51)
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#define INT_ADMA_EOT20 AGIC_IRQ(52)
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#define INT_ADMA_EOT21 AGIC_IRQ(53)
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#define INT_ADMA_EOT22 AGIC_IRQ(54)
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#define INT_ADMA_EOT23 AGIC_IRQ(55)
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#define INT_ADMA_EOT24 AGIC_IRQ(56)
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#define INT_ADMA_EOT25 AGIC_IRQ(57)
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#define INT_ADMA_EOT26 AGIC_IRQ(58)
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#define INT_ADMA_EOT27 AGIC_IRQ(59)
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#define INT_ADMA_EOT28 AGIC_IRQ(60)
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#define INT_ADMA_EOT29 AGIC_IRQ(61)
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#define INT_ADMA_EOT30 AGIC_IRQ(62)
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#define INT_ADMA_EOT31 AGIC_IRQ(63)
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/* AMISC Mailbox Full Interrupts */
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#define INT_AMISC_MBOX_FULL0 AGIC_IRQ(64)
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#define INT_AMISC_MBOX_FULL1 AGIC_IRQ(65)
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#define INT_AMISC_MBOX_FULL2 AGIC_IRQ(66)
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#define INT_AMISC_MBOX_FULL3 AGIC_IRQ(67)
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#define INT_AMISC_MBOX_FULL4 AGIC_IRQ(68)
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#define INT_AMISC_MBOX_FULL5 AGIC_IRQ(69)
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#define INT_AMISC_MBOX_FULL6 AGIC_IRQ(70)
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#define INT_AMISC_MBOX_FULL7 AGIC_IRQ(71)
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/* AMISC Mailbox Empty Interrupts */
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#define INT_AMISC_MBOX_EMPTY0 AGIC_IRQ(72)
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#define INT_AMISC_MBOX_EMPTY1 AGIC_IRQ(73)
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#define INT_AMISC_MBOX_EMPTY2 AGIC_IRQ(74)
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#define INT_AMISC_MBOX_EMPTY3 AGIC_IRQ(75)
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#define INT_AMISC_MBOX_EMPTY4 AGIC_IRQ(76)
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#define INT_AMISC_MBOX_EMPTY5 AGIC_IRQ(77)
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#define INT_AMISC_MBOX_EMPTY6 AGIC_IRQ(78)
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#define INT_AMISC_MBOX_EMPTY7 AGIC_IRQ(79)
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/* AHSP SHARED INTERRUPT */
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#define INT_AHSP_SHRD0 AGIC_IRQ(80)
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#define INT_AHSP_SHRD1 AGIC_IRQ(81)
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#define INT_AHSP_SHRD2 AGIC_IRQ(82)
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#define INT_AHSP_SHRD3 AGIC_IRQ(83)
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#define INT_AHSP_SHRD4 AGIC_IRQ(84)
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/* ADSP/PTM Performance Monitoring Unit Interrupt */
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#define INT_ADSP_PMU AGIC_IRQ(85)
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/* ADSP Watchdog Timer Reset Request */
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#define INT_ADSP_WDT AGIC_IRQ(86)
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/* ADSP L2 Cache Controller Interrupt */
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#define INT_ADSP_L2CC AGIC_IRQ(87)
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/* AHUB Error Interrupt */
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#define INT_AHUB_ERR AGIC_IRQ(88)
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/* AMC Error Interrupt */
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#define INT_AMC_ERR AGIC_IRQ(89)
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/* INT_ADMA Error Interrupt */
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#define INT_ADMA_ERR0 AGIC_IRQ(90)
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#define INT_ADMA_ERR1 AGIC_IRQ(91)
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#define INT_ADMA_ERR2 AGIC_IRQ(92)
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#define INT_ADMA_ERR3 AGIC_IRQ(93)
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/* ADSP Standby WFI. ADSP in idle mode. Waiting for Interrupt */
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#define INT_WFI AGIC_IRQ(94)
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/* ADSP Standby WFE. ADSP in idle mode. Waiting for Event */
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#define INT_WFE AGIC_IRQ(95)
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#define INT_ADSP_CTI AGIC_IRQ(96)
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/* Activity monitoring on ADSP. This interrupt is from AMISC */
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#define INT_ADSP_ACTMON AGIC_IRQ(97)
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#define INT_ADSP_ACTMON_RESERVED0 AGIC_IRQ(98)
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#define INT_ADSP_ACTMON_RESERVED1 AGIC_IRQ(99)
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/* LIC to APE Interrupts */
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#define INT_LIC_TO_APE0 AGIC_IRQ(100)
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#define INT_LIC_TO_APE1 AGIC_IRQ(101)
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/* VI Notify High Interrupt */
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#define INT_VI_NOTIFY_HIGH AGIC_IRQ(102)
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#define INT_VI_NOTIFY_LOW AGIC_IRQ(103)
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/* I2C {1,3,8} Interrupt */
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#define INT_I2C_IRQ1 AGIC_IRQ(104)
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#define INT_I2C_IRQ3 AGIC_IRQ(105)
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#define INT_I2C_IRQ8 AGIC_IRQ(106)
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/* System Door Bell interrupt */
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#define INT_SHSP2APE_DB AGIC_IRQ(107)
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/* Top WDT FIQ interrupt */
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#define INT_TOP_WDT_FIQ AGIC_IRQ(108)
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/* Top WDT IRQ interrupt */
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#define INT_TOP_WDT_IRQ AGIC_IRQ(109)
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/* ATKE Timer IRQ interrupt */
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#define INT_ATKE_TMR0 AGIC_IRQ(110)
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#define INT_ATKE_TMR1 AGIC_IRQ(111)
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#define INT_ATKE_TMR2 AGIC_IRQ(112)
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#define INT_ATKE_TMR3 AGIC_IRQ(113)
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/* ATKE WDT FIQ interrupt */
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#define INT_ATKE_WDT_FIQ AGIC_IRQ(114)
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/* ATKE WDT IRQ interrupt */
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#define INT_ATKE_WDT_IRQ AGIC_IRQ(115)
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/* ATKE WDT error interrupt */
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#define INT_ATKE_WDT_ERR AGIC_IRQ(116)
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/* UART interrupt to AGIC (In FPGA platform only) */
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#define INT_UART_FPGA AGIC_IRQ(117)
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#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_TEGRA_T18X_AGIC_H */
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