Jetpack/hardware/nvidia/platform/tegra/common/kernel-dts/panels/panel-s-wuxga-7-0.dtsi

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/*
* arch/arm/boot/dts/panel-s-wuxga-7-0.dtsi
*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <dt-bindings/display/tegra-dc.h>
#include <dt-bindings/display/tegra-panel.h>
/ {
host1x {
dsi {
panel_s_wuxga_7_0: panel-s-wuxga-7-0 {
status = "disabled";
compatible = "s,wuxga-7-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <8>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP>;
nvidia,dsi-ganged-overlap = <2>;
nvidia,dsi-ganged-swap-links = <1>;
nvidia,dsi-ganged-write-to-all-links = <1>;
nvidia,dsi-controller-vs = <DSI_VS_1>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
nvidia,dsi-suspend-stop-stream-late = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,dsi-init-cmd =
/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
/* For DSI packets each DT cell is interpreted as u8 not u32 */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
/* This panel has a very sensitive power on/off sequence.
* Send a few more frames for safety. No max limit from vendor. */
<TEGRA_DSI_SEND_FRAME 10>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>;
nvidia,dsi-n-init-cmd = <3>;
nvidia,dsi-suspend-cmd =
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
<TEGRA_DSI_SEND_FRAME 3>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_SEND_FRAME 10>;
nvidia,dsi-n-suspend-cmd = <4>;
nvidia,dsi-pkt-seq =
<CMD_VS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
<CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <107>;
nvidia,out-height = <172>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <1200>;
nvidia,out-yres = <1920>;
};
display-timings {
1200x1920-32-60Hz {
clock-frequency = <193224000>;
hactive = <1200>;
vactive = <1920>;
hfront-porch = <107>;
hback-porch = <20>;
hsync-len = <1>;
vfront-porch = <497>;
vback-porch = <7>;
vsync-len = <1>;
nvidia,h-ref-to-sync = <1>;
nvidia,v-ref-to-sync = <11>;
};
};
smartdimmer {
status = "okay";
nvidia,use-auto-pwm = <0>;
nvidia,hw-update-delay = <0>;
nvidia,bin-width = <0xffffffff>;
nvidia,aggressiveness = <5>;
nvidia,use-vid-luma = <0>;
nvidia,phase-in-settings = <0>;
nvidia,phase-in-adjustments = <0>;
nvidia,k-limit-enable = <1>;
nvidia,k-limit = <200>;
nvidia,sd-window-enable = <0>;
nvidia,soft-clipping-enable= <1>;
nvidia,soft-clipping-threshold = <128>;
nvidia,smooth-k-enable = <1>;
nvidia,smooth-k-incr = <4>;
nvidia,coeff = <5 9 2>;
nvidia,fc = <0 0>;
nvidia,blp = <1024 255>;
nvidia,bltf = <57 65 73 82
92 103 114 125
138 150 164 178
193 208 224 241>;
nvidia,lut = <255 255 255
199 199 199
153 153 153
116 116 116
85 85 85
59 59 59
36 36 36
17 17 17
0 0 0>;
nvidia,use-vpulse2 = <1>;
nvidia,bl-device-name = "pwm-backlight";
};
cmu {
nvidia,cmu-csc = < 0x100 0x0 0x0
0x0 0x100 0x0
0x0 0x0 0x100 >;
nvidia,cmu-lut2 = < 0 1 2 2 3 4 5 6
6 7 8 9 10 10 11 12
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105 105 106 107 107 108 109 109
110 111 111 112 113 113 114 115
115 116 116 117 118 118 119 119
120 120 121 122 122 123 123 124
124 125 126 126 127 127 128 128
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141 141 142 142 143 143 144 144
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248 248 248 249 249 249 249 249
250 250 250 250 251 251 251 251
251 252 252 252 252 253 253 253
253 253 254 254 254 254 255 255 >;
};
};
};
};
backlight {
panel_s_wuxga_7_0_bl: panel-s-wuxga-7-0-bl {
status = "disabled";
compatible = "s,wuxga-7-0-bl";
pwms = <&tegra_pwm 1 40161>;
max-brightness = <255>;
default-brightness = <191>;
default-charge-brightness = <112>;
bl-measured = < 0 1 2 4 5 6 7 8
10 11 12 13 14 15 16 18
19 20 21 22 23 24 25 26
27 29 30 31 32 33 34 35
36 38 39 40 41 42 44 45
46 47 48 49 50 52 53 54
55 56 57 58 59 61 62 63
64 65 67 68 69 70 71 72
73 75 76 77 78 79 80 81
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90 91 92 93 94 96 97 98
99 100 101 102 103 104 105 106
107 108 109 110 111 112 112 113
114 115 115 116 117 117 118 119
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221 222 223 224 225 226 227 228
229 230 231 232 233 234 235 235
236 237 238 239 240 241 242 243
244 245 247 248 249 250 251 251
252 252 253 253 254 254 255 255 >;
};
};
};