forked from rrcarlosr/Jetpack
336 lines
8.5 KiB
C
336 lines
8.5 KiB
C
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/*
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* (C) Copyright 2007-2010 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/xilinx/microblaze-generic/xparameters.h"
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/* MicroBlaze CPU */
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#define MICROBLAZE_V5 1
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/* linear and spi flash memory */
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#ifdef XILINX_FLASH_START
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#define FLASH
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#undef SPIFLASH
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#undef RAMENV /* hold environment in flash */
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#else
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#ifdef XILINX_SPI_FLASH_BASEADDR
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#undef FLASH
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#define SPIFLASH
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#undef RAMENV /* hold environment in flash */
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#else
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#undef FLASH
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#undef SPIFLASH
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#define RAMENV /* hold environment in RAM */
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#endif
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#endif
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/* uart */
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# define CONFIG_BAUDRATE 115200
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/* The following table includes the supported baudrates */
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# define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/* setting reset address */
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/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
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/* gpio */
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#ifdef XILINX_GPIO_BASEADDR
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# define CONFIG_XILINX_GPIO
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# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
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#endif
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#define CONFIG_BOARD_LATE_INIT
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/* watchdog */
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#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
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# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
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# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
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# ifndef CONFIG_SPL_BUILD
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# define CONFIG_HW_WATCHDOG
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# define CONFIG_XILINX_TB_WATCHDOG
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# endif
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#endif
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#define CONFIG_SYS_MALLOC_LEN 0xC0000
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/* Stack location before relocation */
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SYS_MALLOC_F_LEN)
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/*
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* CFI flash memory layout - Example
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* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
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* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
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*
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* SECT_SIZE = 0x20000; 128kB is one sector
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* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
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*
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* 0x2200_0000 CONFIG_SYS_FLASH_BASE
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* FREE 256kB
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* 0x2204_0000 CONFIG_ENV_ADDR
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* ENV_AREA 128kB
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* 0x2206_0000
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* FREE
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* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
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*
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*/
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#ifdef FLASH
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# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
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# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
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# define CONFIG_SYS_FLASH_CFI 1
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# define CONFIG_FLASH_CFI_DRIVER 1
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/* ?empty sector */
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# define CONFIG_SYS_FLASH_EMPTY_INFO 1
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/* max number of memory banks */
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# define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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# define CONFIG_SYS_MAX_FLASH_SECT 512
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/* hardware flash protection */
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# define CONFIG_SYS_FLASH_PROTECTION
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/* use buffered writes (20x faster) */
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# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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# ifdef RAMENV
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# define CONFIG_ENV_IS_NOWHERE 1
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# define CONFIG_ENV_SIZE 0x1000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
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# else /* FLASH && !RAMENV */
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# define CONFIG_ENV_IS_IN_FLASH 1
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/* 128K(one sector) for env */
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# define CONFIG_ENV_SECT_SIZE 0x20000
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# define CONFIG_ENV_ADDR \
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(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
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# define CONFIG_ENV_SIZE 0x20000
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# endif /* FLASH && !RAMBOOT */
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#else /* !FLASH */
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#ifdef SPIFLASH
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# define CONFIG_SYS_NO_FLASH 1
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# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
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# define CONFIG_SPI 1
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# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
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# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
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# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
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# ifdef RAMENV
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# define CONFIG_ENV_IS_NOWHERE 1
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# define CONFIG_ENV_SIZE 0x1000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
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# else /* SPIFLASH && !RAMENV */
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# define CONFIG_ENV_IS_IN_SPI_FLASH 1
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# define CONFIG_ENV_SPI_MODE SPI_MODE_3
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# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
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/* 128K(two sectors) for env */
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# define CONFIG_ENV_SECT_SIZE 0x10000
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# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
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/* Warning: adjust the offset in respect of other flash content and size */
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# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
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# endif /* SPIFLASH && !RAMBOOT */
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#else /* !SPIFLASH */
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/* ENV in RAM */
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# define CONFIG_SYS_NO_FLASH 1
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# define CONFIG_ENV_IS_NOWHERE 1
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# define CONFIG_ENV_SIZE 0x1000
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
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#endif /* !SPIFLASH */
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#endif /* !FLASH */
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#if defined(XILINX_USE_ICACHE)
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# define CONFIG_ICACHE
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#else
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# undef CONFIG_ICACHE
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#endif
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#if defined(XILINX_USE_DCACHE)
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# define CONFIG_DCACHE
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#else
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# undef CONFIG_DCACHE
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#endif
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#ifndef XILINX_DCACHE_BYTE_SIZE
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#define XILINX_DCACHE_BYTE_SIZE 32768
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MFSL
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#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
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#else
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#endif
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#if defined(FLASH)
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# define CONFIG_CMD_JFFS2
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# define CONFIG_CMD_UBI
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# undef CONFIG_CMD_UBIFS
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# if !defined(RAMENV)
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# define CONFIG_CMD_SAVES
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# endif
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#else
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#if defined(SPIFLASH)
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# if !defined(RAMENV)
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# define CONFIG_CMD_SAVES
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# endif
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#else
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# undef CONFIG_CMD_JFFS2
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# undef CONFIG_CMD_UBI
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# undef CONFIG_CMD_UBIFS
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#endif
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#endif
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#if defined(CONFIG_CMD_JFFS2)
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# define CONFIG_MTD_PARTITIONS
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#endif
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#if defined(CONFIG_CMD_UBIFS)
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# define CONFIG_CMD_UBI
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# define CONFIG_LZO
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#endif
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#if defined(CONFIG_CMD_UBI)
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# define CONFIG_MTD_PARTITIONS
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# define CONFIG_RBTREE
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#endif
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#if defined(CONFIG_MTD_PARTITIONS)
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/* MTD partitions */
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#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=flash-0"
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/* default mtd partition table */
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#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
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"256k(env),3m(kernel),1m(romfs),"\
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"1m(cramfs),-(jffs2)"
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#endif
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/* size of console buffer */
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#define CONFIG_SYS_CBSIZE 512
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/* print buffer size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 15
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#define CONFIG_SYS_LONGHELP
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0
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#define CONFIG_BOOTARGS "root=romfs"
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#define CONFIG_HOSTNAME XILINX_BOARD_NAME
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#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
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#define CONFIG_IPADDR 192.168.0.3
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#define CONFIG_SERVERIP 192.168.0.5
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#define CONFIG_GATEWAYIP 192.168.0.1
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/* architecture dependent code */
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#define CONFIG_SYS_USR_EXCEP /* user exception */
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#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
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#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
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"nor0=flash-0\0"\
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"mtdparts=mtdparts=flash-0:"\
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"256k(u-boot),256k(env),3m(kernel),"\
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"1m(romfs),1m(cramfs),-(jffs2)\0"\
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"nc=setenv stdout nc;"\
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"setenv stdin nc\0" \
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"serial=setenv stdout serial;"\
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"setenv stdin serial\0"
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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/* Enable flat device tree support */
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#define CONFIG_LMB 1
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#if defined(CONFIG_XILINX_AXIEMAC)
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# define CONFIG_MII 1
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# define CONFIG_PHY_GIGE 1
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
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# define CONFIG_PHY_ATHEROS 1
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# define CONFIG_PHY_BROADCOM 1
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# define CONFIG_PHY_DAVICOM 1
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# define CONFIG_PHY_LXT 1
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# define CONFIG_PHY_MARVELL 1
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# define CONFIG_PHY_MICREL 1
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# define CONFIG_PHY_MICREL_KSZ9021
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# define CONFIG_PHY_NATSEMI 1
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# define CONFIG_PHY_REALTEK 1
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# define CONFIG_PHY_VITESSE 1
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#else
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# undef CONFIG_MII
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#endif
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/* SPL part */
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#define CONFIG_CMD_SPL
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
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#define CONFIG_SPL_RAM_DEVICE
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#ifdef CONFIG_SYS_FLASH_BASE
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# define CONFIG_SPL_NOR_SUPPORT
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# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
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#endif
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/* for booting directly linux */
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#define CONFIG_SPL_OS_BOOT
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#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
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0x60000)
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#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
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0x40000)
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
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0x1000000)
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/* SP location before relocation, must use scratch RAM */
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/* BRAM start */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x0
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/* BRAM size - will be generated */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
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# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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CONFIG_SYS_MALLOC_F_LEN)
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/* Just for sure that there is a space for stack */
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#define CONFIG_SPL_STACK_SIZE 0x100
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
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CONFIG_SYS_INIT_RAM_ADDR - \
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CONFIG_SYS_MALLOC_F_LEN - \
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CONFIG_SPL_STACK_SIZE)
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#endif /* __CONFIG_H */
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