forked from rrcarlosr/Jetpack
305 lines
12 KiB
C
305 lines
12 KiB
C
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/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */
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#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME bubinga
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_NO_SERIAL_EEPROM
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/*#undef CONFIG_NO_SERIAL_EEPROM*/
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/*----------------------------------------------------------------------------*/
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#ifdef CONFIG_NO_SERIAL_EEPROM
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/*
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!-------------------------------------------------------------------------------
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! Defines for entry options.
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! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
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! are plugged in the board will be utilized as non-ECC DIMMs.
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!-------------------------------------------------------------------------------
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*/
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#define AUTO_MEMORY_CONFIG
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#define DIMM_READ_ADDR 0xAB
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#define DIMM_WRITE_ADDR 0xAA
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/*
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!-------------------------------------------------------------------------------
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! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
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! assuming a 33MHz input clock to the 405EP from the C9531.
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!-------------------------------------------------------------------------------
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*/
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#define PLLMR0_DEFAULT PLLMR0_266_133_66
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#define PLLMR1_DEFAULT PLLMR1_266_133_66
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#endif
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/*----------------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or NVRAM).
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* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
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* supported for backward compatibility.
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*/
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#if 1
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#endif
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_PPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fff80000\0" \
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"ramdisk_addr=fff90000\0" \
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""
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
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#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
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/*
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* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CONFIG_SYS_BASE_BAUD 691200
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/*-----------------------------------------------------------------------
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* I2C stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#if defined(CONFIG_CMD_EEPROM)
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
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#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
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#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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*/
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#define CONFIG_SYS_SRAM_BASE 0xFFF00000
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#define CONFIG_SYS_SRAM_SIZE (256 << 10)
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#define CONFIG_SYS_FLASH_BASE 0xFFF80000
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_ADDR0 0x5555
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#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
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#ifdef CONFIG_ENV_IS_IN_NVRAM
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#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
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#endif
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Flash/SRAM) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x04006000
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#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 1 (NVRAM/RTC) initialization */
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#define CONFIG_SYS_EBC_PB1AP 0x04041000
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#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 2 (not used) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x00000000
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#define CONFIG_SYS_EBC_PB2CR 0x00000000
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/* Memory Bank 2 (not used) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x00000000
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#define CONFIG_SYS_EBC_PB3CR 0x00000000
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/* Memory Bank 4 (FPGA regs) initialization */
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#define CONFIG_SYS_EBC_PB4AP 0x01815000
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#define CONFIG_SYS_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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*/
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#define SPD_EEPROM_ADDRESS 0x55
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/*-----------------------------------------------------------------------
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* Definitions for GPIO setup (PPC405EP specific)
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*
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* GPIO0[0] - External Bus Controller BLAST output
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* GPIO0[1-9] - Instruction trace outputs
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* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
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* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
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* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
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* GPIO0[24-27] - UART0 control signal inputs/outputs
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
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*/
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#define CONFIG_SYS_GPIO0_OSRL 0x55555555
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#define CONFIG_SYS_GPIO0_OSRH 0x40000110
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#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
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#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
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#define CONFIG_SYS_GPIO0_TSRL 0x00000000
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#define CONFIG_SYS_GPIO0_TSRH 0x00000000
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#define CONFIG_SYS_GPIO0_TCR 0xFFFF8014
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/*-----------------------------------------------------------------------
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* Some BUBINGA stuff...
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*/
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#define NVRAM_BASE 0xF0000000
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#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
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#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
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#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
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#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
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#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
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#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
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#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
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#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
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#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
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#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
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#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
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#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
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#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
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#define FPGA_REG1_CLOCK_BIT_SHIFT 4
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#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
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#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
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#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
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#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
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#endif /* __CONFIG_H */
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