forked from rrcarlosr/Jetpack
399 lines
15 KiB
C
399 lines
15 KiB
C
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/*
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* (C) Copyright 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/***********************************************************
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* High Level Configuration Options
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* (easy to change)
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***********************************************************/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_MIP405 1 /* ...on a MIP405 board */
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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/***********************************************************
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* Note that it may also be a MIP405T board which is a subset of the
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* MIP405
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***********************************************************/
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/***********************************************************
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* WARNING:
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* CONFIG_BOOT_PCI is only used for first boot-up and should
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* NOT be enabled for production bootloader
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***********************************************************/
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/*#define CONFIG_BOOT_PCI 1*/
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/***********************************************************
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* Clock
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***********************************************************/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_BSP
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#if !defined(CONFIG_MIP405T)
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#endif
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/**************************************************************
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* I2C Stuff:
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* the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
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* 0x53.
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* The Atmel EEPROM uses 16Bit addressing.
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***************************************************************/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_PPC4XX
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#define CONFIG_SYS_I2C_PPC4XX_CH0
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
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#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
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/* 64 byte page write mode using*/
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/* last 6 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
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#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
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/***************************************************************
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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***************************************************************/
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/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
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#define SDRAM_EEPROM_READ_ADDRESS 0xA1
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*/
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/**************************************************************
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* Environment definitions
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**************************************************************/
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#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
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/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
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/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
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#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
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#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
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#define CONFIG_IPADDR 10.0.0.100
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#define CONFIG_SERVERIP 10.0.0.1
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#define CONFIG_PREBOOT
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/***************************************************************
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* defines if the console is stored in the environment
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***************************************************************/
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
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/***************************************************************
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* defines if an overwrite_console function exists
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*************************************************************/
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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/***************************************************************
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* defines if the overwrite_console should be stored in the
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* environment
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**************************************************************/
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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/**************************************************************
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* loads config
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*************************************************************/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MISC_INIT_R
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/***********************************************************
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* Miscellaneous configurable options
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**********************************************************/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CONFIG_SYS_BASE_BAUD 916667
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
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#define CONFIG_PCI_PNP /* pci plug-and-play */
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/* resource configuration */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFF80000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_UPDATE_FLASH_SIZE
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Note: fake mtd_id used, no linux mtd map file */
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/*
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#define CONFIG_CMD_MTDPARTS
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#define MTDIDS_DEFAULT "nor0=mip405-0"
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#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
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*/
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/*-----------------------------------------------------------------------
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* Logbuffer Configuration
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*/
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#undef CONFIG_LOGBUFFER /* supported but not enabled */
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/*-----------------------------------------------------------------------
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* Bootcountlimit Configuration
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*/
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#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
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/*-----------------------------------------------------------------------
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* POST Configuration
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*/
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#if 0 /* enable this if POST is desired (is supported but not enabled) */
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_RTC | \
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CONFIG_SYS_POST_I2C)
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#endif
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/*
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* Init Memory Controller:
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*/
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#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
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#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_BOARD_EARLY_INIT_R
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/* Peripheral Bus Mapping */
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#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
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#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
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#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
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#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
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#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in On Chip SRAM)
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*/
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/* reserve some memory for POST and BOOT limit info */
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
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#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
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#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
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#endif
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/***********************************************************************
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* External peripheral base address
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***********************************************************************/
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
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/***********************************************************************
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* Last Stage Init
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***********************************************************************/
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#define CONFIG_LAST_STAGE_INIT
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/************************************************************
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* Ethernet Stuff
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***********************************************************/
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
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#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
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/************************************************************
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* RTC
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***********************************************************/
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#define CONFIG_RTC_MC146818
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/************************************************************
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* IDE/ATA stuff
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************************************************************/
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#if defined(CONFIG_MIP405T)
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#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
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#else
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#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
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#endif
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#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
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#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET /* reset for ide supported... */
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#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
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#define CONFIG_SUPPORT_VFAT
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/************************************************************
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* ATAPI support (experimental)
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************************************************************/
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#define CONFIG_ATAPI /* enable ATAPI Support */
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/************************************************************
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* DISK Partition support
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************************************************************/
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#define CONFIG_DOS_PARTITION
|
||
|
|
#define CONFIG_MAC_PARTITION
|
||
|
|
#define CONFIG_ISO_PARTITION /* Experimental */
|
||
|
|
|
||
|
|
/************************************************************
|
||
|
|
* Video support
|
||
|
|
************************************************************/
|
||
|
|
#define CONFIG_VIDEO /*To enable video controller support */
|
||
|
|
#define CONFIG_VIDEO_CT69000
|
||
|
|
#define CONFIG_CFB_CONSOLE
|
||
|
|
#define CONFIG_VIDEO_LOGO
|
||
|
|
#define CONFIG_CONSOLE_EXTRA_INFO
|
||
|
|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||
|
|
#define CONFIG_VIDEO_SW_CURSOR
|
||
|
|
#undef CONFIG_VIDEO_ONBOARD
|
||
|
|
/************************************************************
|
||
|
|
* USB support EXPERIMENTAL
|
||
|
|
************************************************************/
|
||
|
|
#if !defined(CONFIG_MIP405T)
|
||
|
|
#define CONFIG_USB_UHCI
|
||
|
|
#define CONFIG_USB_KEYBOARD
|
||
|
|
#define CONFIG_USB_STORAGE
|
||
|
|
|
||
|
|
/* Enable needed helper functions */
|
||
|
|
#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
|
||
|
|
#endif
|
||
|
|
/************************************************************
|
||
|
|
* Debug support
|
||
|
|
************************************************************/
|
||
|
|
#if defined(CONFIG_CMD_KGDB)
|
||
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/************************************************************
|
||
|
|
* support BZIP2 compression
|
||
|
|
************************************************************/
|
||
|
|
#define CONFIG_BZIP2 1
|
||
|
|
|
||
|
|
/************************************************************
|
||
|
|
* Ident
|
||
|
|
************************************************************/
|
||
|
|
|
||
|
|
#define VERSION_TAG "released"
|
||
|
|
#if !defined(CONFIG_MIP405T)
|
||
|
|
#define CONFIG_ISO_STRING "MEV-10072-001"
|
||
|
|
#else
|
||
|
|
#define CONFIG_ISO_STRING "MEV-10082-001"
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if !defined(CONFIG_BOOT_PCI)
|
||
|
|
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
|
||
|
|
#else
|
||
|
|
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __CONFIG_H */
|