forked from rrcarlosr/Jetpack
76 lines
1.7 KiB
C
76 lines
1.7 KiB
C
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/*
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* Copyright (c) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/pch.h>
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int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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return -ENOSYS;
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}
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int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags)
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{
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return -ENOSYS;
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}
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int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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return 0;
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}
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static int intel_i2c_probe(struct udevice *dev)
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{
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/*
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* So far this is just setup code for ivybridge SMbus. When we have
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* a full I2C driver this may need to be moved, generalised or made
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* dependant on a particular compatible string.
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*
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* Set SMBus I/O base
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*/
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dm_pci_write_config32(dev, SMB_BASE,
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SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
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/* Set SMBus enable. */
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dm_pci_write_config8(dev, HOSTC, HST_EN);
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/* Set SMBus I/O space enable. */
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dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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/* Disable interrupt generation. */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* Clear any lingering errors, so transactions can run. */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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debug("SMBus controller enabled\n");
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return 0;
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}
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static const struct dm_i2c_ops intel_i2c_ops = {
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.xfer = intel_i2c_xfer,
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.probe_chip = intel_i2c_probe_chip,
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.set_bus_speed = intel_i2c_set_bus_speed,
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};
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static const struct udevice_id intel_i2c_ids[] = {
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{ .compatible = "intel,ich-i2c" },
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{ }
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};
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U_BOOT_DRIVER(intel_i2c) = {
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.name = "i2c_intel",
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.id = UCLASS_I2C,
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.of_match = intel_i2c_ids,
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.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
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.ops = &intel_i2c_ops,
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.probe = intel_i2c_probe,
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};
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