forked from rrcarlosr/Jetpack
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
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/*
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* Author Adrian Cox
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* Based somewhat on board/freescale/corenet_ds/eth_hydra.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/fsl_serdes.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fdt_support.h>
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#include <fsl_dtsec.h>
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#ifdef CONFIG_FMAN_ENET
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#define FIRST_PORT_ADDR 3
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#define SECOND_PORT_ADDR 7
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#ifdef CONFIG_PPC_P5040
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#define FIRST_PORT FM1_DTSEC5
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#define SECOND_PORT FM2_DTSEC5
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#else
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#define FIRST_PORT FM1_DTSEC4
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#define SECOND_PORT FM1_DTSEC5
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#endif
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#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
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static void cyrus_phy_tuning(int phy)
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{
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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*/
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printf("Tuning PHY @ %d\n", phy);
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/* sets address 0x104 or reg 260 for writing */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
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/* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
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/* sets address 0x105 or reg 261 for writing */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
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/* writes to address 0x105 , RXD[3..0] to -0. */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
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/* sets address 0x106 or reg 261 for writing */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
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/* writes to address 0x106 , TXD[3..0] to -0.84ns */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
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/* force re-negotiation */
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miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct fsl_pq_mdio_info dtsec_mdio_info;
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unsigned int i;
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printf("Initializing Fman\n");
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/* Register the real 1G MDIO bus */
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dtsec_mdio_info.regs =
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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fsl_pq_mdio_init(bis, &dtsec_mdio_info);
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fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
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fm_info_set_mdio(FIRST_PORT,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
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fm_info_set_mdio(SECOND_PORT,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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/* Never disable DTSEC1 - it controls MDIO */
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for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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if (!IS_VALID_PORT(i))
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fm_disable_port(i);
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}
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#ifdef CONFIG_PPC_P5040
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for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
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if (!IS_VALID_PORT(i))
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fm_disable_port(i);
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}
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#endif
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cpu_eth_init(bis);
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cyrus_phy_tuning(FIRST_PORT_ADDR);
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cyrus_phy_tuning(SECOND_PORT_ADDR);
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#endif
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return pci_eth_init(bis);
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}
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