forked from rrcarlosr/Jetpack
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __T1040QDS_QIXIS_H__
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#define __T1040QDS_QIXIS_H__
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/* Definitions of QIXIS Registers for T1040QDS */
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
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#define BRDCFG4_EMISEL_MASK 0xE0
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#define BRDCFG4_EMISEL_SHIFT 5
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/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
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#define BRDCFG5_IMX_MASK 0xC0
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#define BRDCFG5_IMX_DIU 0x80
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/* BRDCFG9[2] controls EPHY2 Clock */
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#define BRDCFG9_EPHY2_MASK 0x20
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#define BRDCFG9_EPHY2_VAL 0x00
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/* BRDCFG15[3] controls LCD Panel Powerdown*/
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#define BRDCFG15_LCDPD_MASK 0x10
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#define BRDCFG15_LCDPD_ENABLED 0x00
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/* BRDCFG15[6:7] controls DIU MUX selction*/
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#define BRDCFG15_DIUSEL_MASK 0x03
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#define BRDCFG15_DIUSEL_HDMI 0x00
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/* SYSCLK */
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#define QIXIS_SYSCLK_66 0x0
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#define QIXIS_SYSCLK_83 0x1
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#define QIXIS_SYSCLK_100 0x2
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#define QIXIS_SYSCLK_125 0x3
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#define QIXIS_SYSCLK_133 0x4
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#define QIXIS_SYSCLK_150 0x5
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#define QIXIS_SYSCLK_160 0x6
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#define QIXIS_SYSCLK_166 0x7
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#define QIXIS_SYSCLK_64 0x8
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/* DDRCLK */
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#define QIXIS_DDRCLK_66 0x0
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#define QIXIS_DDRCLK_100 0x1
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#define QIXIS_DDRCLK_125 0x2
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#define QIXIS_DDRCLK_133 0x3
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#define QIXIS_SRDS1CLK_122 0x5a
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#define QIXIS_SRDS1CLK_125 0x5e
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#endif
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