forked from rrcarlosr/Jetpack
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
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/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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int board_early_init_f(void)
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{
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the Walnut/Sycamore board.
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
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| IRQ 16 405GP internally generated; active low; level sensitive
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| IRQ 17-24 RESERVED
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| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
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| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
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| IRQ 27 (EXT IRQ 2) Not Used
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
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| Note for Walnut board:
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| An interrupt taken for the FPGA (IRQ 25) indicates that either
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| the Mouse, Keyboard, IRDA, or External Expansion caused the
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| interrupt. The FPGA must be read to determine which device
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| caused the interrupt. The default setting of the FPGA clears
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+-------------------------------------------------------------------------*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
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mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/* set UART1 control to select CTS/RTS */
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#define FPGA_BRDC 0xF0300004
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*(volatile char *)(FPGA_BRDC) |= 0x1;
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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uint pvr = get_pvr();
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if (pvr == PVR_405GPR_RB) {
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puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
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} else {
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puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
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}
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return (0);
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}
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/*
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* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
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* the necessary info for SDRAM controller configuration
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*/
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phys_size_t initdram(int board_type)
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{
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return spd_sdram();
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}
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