forked from rrcarlosr/Jetpack
177 lines
6.6 KiB
C
177 lines
6.6 KiB
C
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/*
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* drivers/misc/tegra-cec/tegra_cec.h
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*
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* Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_CEC_H
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#define TEGRA_CEC_H
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#include <linux/pm.h>
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#include <asm/atomic.h>
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#define TEGRA_CEC_FRAME_MAX_LENGTH 16
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struct tegra_cec_soc;
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struct tegra_cec {
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struct device *dev;
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struct miscdevice misc_dev;
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struct clk *clk;
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struct mutex tx_lock;
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struct mutex recovery_lock;
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void __iomem *cec_base;
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int tegra_cec_irq;
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wait_queue_head_t rx_waitq;
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wait_queue_head_t tx_waitq;
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wait_queue_head_t init_waitq;
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atomic_t init_done;
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#ifdef CONFIG_PM
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wait_queue_head_t suspend_waitq;
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atomic_t init_cancel;
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#endif
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u16 logical_addr;
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struct work_struct work;
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const struct tegra_cec_soc *soc;
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unsigned int rx_wake;
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unsigned int tx_wake;
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u16 rx_buffer;
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long tx_error;
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u32 tx_buf[TEGRA_CEC_FRAME_MAX_LENGTH];
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u8 tx_buf_cur;
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u8 tx_buf_cnt;
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};
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static int tegra_cec_remove(struct platform_device *pdev);
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#define TEGRA_CEC_LADDR_BROADCAST 0xF
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#define TEGRA_CEC_LADDR_MASK 0xF
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#define TEGRA_CEC_LADDR_WIDTH 4
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#define TEGRA_CEC_LADDR_MODE(blk) \
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((blk & TEGRA_CEC_LADDR_MASK) == TEGRA_CEC_LADDR_BROADCAST)
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/*CEC Timing registers*/
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#define TEGRA_CEC_SW_CONTROL 0X000
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#define TEGRA_CEC_HW_CONTROL 0X004
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#define TEGRA_CEC_INPUT_FILTER 0X008
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#define TEGRA_CEC_TX_REGISTER 0X010
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#define TEGRA_CEC_RX_REGISTER 0X014
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#define TEGRA_CEC_RX_TIMING_0 0X018
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#define TEGRA_CEC_RX_TIMING_1 0X01C
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#define TEGRA_CEC_RX_TIMING_2 0X020
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#define TEGRA_CEC_TX_TIMING_0 0X024
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#define TEGRA_CEC_TX_TIMING_1 0X028
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#define TEGRA_CEC_TX_TIMING_2 0X02C
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#define TEGRA_CEC_INT_STAT 0X030
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#define TEGRA_CEC_INT_MASK 0X034
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#define TEGRA_CEC_HW_DEBUG_RX 0X038
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#define TEGRA_CEC_HW_DEBUG_TX 0X03C
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#define TEGRA_CEC_HW_SPARE 0X040
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#define TEGRA_CEC_MAX_LOGICAL_ADDR 15
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#define TEGRA_CEC_HWCTRL_RX_LADDR_UNREG 0x0
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#define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7FFF
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#define TEGRA_CEC_HWCTRL_RX_LADDR(x) \
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((x<<0) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK)
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#define TEGRA_CEC_HWCTRL_RX_SNOOP (1<<15)
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#define TEGRA_CEC_HWCTRL_RX_NAK_MODE (1<<16)
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#define TEGRA_CEC_HWCTRL_TX_NAK_MODE (1<<24)
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#define TEGRA_CEC_HWCTRL_FAST_SIM_MODE (1<<30)
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#define TEGRA_CEC_HWCTRL_TX_RX_MODE (1<<31)
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#define TEGRA_CEC_INPUT_FILTER_MODE (1<<31)
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#define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_MASK 0
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#define TEGRA_CEC_TX_REG_DATA_SHIFT 0
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#define TEGRA_CEC_TX_REG_EOM_SHIFT 8
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#define TEGRA_CEC_TX_REG_ADDR_MODE_SHIFT 12
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#define TEGRA_CEC_TX_REG_START_BIT_SHIFT 16
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#define TEGRA_CEC_TX_REG_RETRY_BIT_SHIFT 17
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#define TEGRA_CEC_RX_REGISTER_MASK 0
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#define TEGRA_CEC_RX_REGISTER_EOM (1<<8)
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#define TEGRA_CEC_RX_REGISTER_ACK (1<<9)
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#define TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MAX_LO_TIME_MASK 0
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#define TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MIN_LO_TIME_MASK 8
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#define TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MAX_DURATION_MASK 16
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#define TEGRA_CEC_RX_TIMING_0_RX_START_BIT_MIN_DURATION_MASK 24
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#define TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_MAX_LO_TIME_MASK 0
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#define TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_SAMPLE_TIME_MASK 8
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#define TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_MAX_DURATION_MASK 16
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#define TEGRA_CEC_RX_TIMING_1_RX_DATA_BIT_MIN_DURATION_MASK 24
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#define TEGRA_CEC_RX_TIMING_2_RX_END_OF_BLOCK_TIME_MASK 0
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#define TEGRA_CEC_TX_TIMING_0_TX_START_BIT_LO_TIME_MASK 0
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#define TEGRA_CEC_TX_TIMING_0_TX_START_BIT_DURATION_MASK 8
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#define TEGRA_CEC_TX_TIMING_0_TX_BUS_XITION_TIME_MASK 16
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#define TEGRA_CEC_TX_TIMING_0_TX_BUS_ERROR_LO_TIME_MASK 24
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#define TEGRA_CEC_TX_TIMING_1_TX_LO_DATA_BIT_LO_TIME_MASK 0
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#define TEGRA_CEC_TX_TIMING_1_TX_HI_DATA_BIT_LO_TIME_MASK 8
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#define TEGRA_CEC_TX_TIMING_1_TX_DATA_BIT_DURATION_MASK 16
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#define TEGRA_CEC_TX_TIMING_1_TX_ACK_NAK_BIT_SAMPLE_TIME_MASK 24
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#define TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_ADDITIONAL_FRAME_MASK 0
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#define TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_NEW_FRAME_MASK 4
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#define TEGRA_CEC_TX_TIMING_2_BUS_IDLE_TIME_RETRY_FRAME_MASK 8
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#define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY (1<<0)
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#define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN (1<<1)
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#define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD (1<<2)
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#define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED (1<<3)
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#define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED (1<<4)
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#define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED (1<<5)
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#define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL (1<<8)
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#define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN (1<<9)
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#define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED (1<<10)
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#define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED (1<<11)
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#define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED (1<<12)
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#define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1<<13)
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#define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1<<14)
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#define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY (1<<0)
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#define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN (1<<1)
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#define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD (1<<2)
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#define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED (1<<3)
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#define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED (1<<4)
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#define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED (1<<5)
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#define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL (1<<8)
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#define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN (1<<9)
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#define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED (1<<10)
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#define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED (1<<11)
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#define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED (1<<12)
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#define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1<<13)
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#define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1<<14)
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#define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_MASK 0
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#define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_MASK 17
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#define TEGRA_CEC_HW_DEBUG_TX_STATE_MASK 21
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#define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT (1<<25)
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#define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER (1<<26)
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#define TEGRA_CEC_NAME "tegra_cec"
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#define TEGRA_CEC_IOC_MAGIC 'C'
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#define TEGRA_CEC_IOCTL_ERROR_RECOVERY _IO(TEGRA_CEC_IOC_MAGIC, 1)
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#define TEGRA_CEC_IOCTL_DUMP_REGISTERS _IO(TEGRA_CEC_IOC_MAGIC, 2)
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#define TEGRA_CEC_IOCTL_SET_RX_SNOOP _IO(TEGRA_CEC_IOC_MAGIC, 3)
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#define TEGRA_CEC_IOCTL_GET_RX_SNOOP _IO(TEGRA_CEC_IOC_MAGIC, 4)
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#define TEGRA_CEC_IOCTL_GET_POST_RECOVERY _IO(TEGRA_CEC_IOC_MAGIC, 5)
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#endif /* TEGRA_CEC_H */
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