forked from rrcarlosr/Jetpack
76 lines
2.4 KiB
Plaintext
76 lines
2.4 KiB
Plaintext
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/*
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* arch/arm/boot/dts/panel-p-edp-3000-2000-13-5.dtsi
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <dt-bindings/display/tegra-dc.h>
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#include <dt-bindings/display/tegra-panel.h>
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/ {
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host1x {
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sor2 {
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panel_p_edp_3000_2000_13_5: panel-p-edp-3000-2000-13-5 {
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status = "disabled";
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compatible = "p-edp,3000-2000-13-5";
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nvidia,tx-pu-disable = <1>;
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backlight = <&lp8556_backlight>;
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disp-default-out {
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nvidia,is_ext_dp_panel=<0>;
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nvidia,out-type = <TEGRA_DC_OUT_DP>;
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nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
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nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
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nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
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nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
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TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
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TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
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TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
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nvidia,out-depth = <24>;
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nvidia,out-width = <285>;
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nvidia,out-height = <190>;
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nvidia,out-xres = <3000>;
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nvidia,out-yres = <2000>;
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nvidia,out-rotation = <180>;
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};
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display-timings {
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3000x2000-60HZ {
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clock-frequency = <417000000>;
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hactive = <3000>;
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vactive = <2000>;
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hfront-porch = <8>;
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hback-porch = <344>;
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hsync-len = <8>;
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vfront-porch = <8>;
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vback-porch = <48>;
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vsync-len = <8>;
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nvidia,h-ref-to-sync = <1>;
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nvidia,v-ref-to-sync = <1>;
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};
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};
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};
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};
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};
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backlight {
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panel_p_edp_3000_2000_13_5_bl: panel-p-edp-3000-2000-13-5-bl {
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status = "okay";
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compatible = "p-edp,3000-2000-13-5-bl";
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pwms = <&tegra_pwm4 0 40161>;
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max-brightness = <255>;
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default-brightness = <224>;
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};
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};
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};
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