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ucans32k1: SPLLDIV2 set to 40Mhz

This commit is contained in:
Peter van der Perk 2023-11-14 09:33:23 +01:00 committed by David Sidrane
parent 50d9d05c10
commit 96e05481b4
1 changed files with 3 additions and 3 deletions
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6
boards/nxp/ucans32k146/src/clockconfig.c
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@ -109,10 +109,10 @@ const struct clock_configuration_s g_initial_clkconfig = {
.spll =
{
.mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_2, /* SPLLDIV2 */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_2, /* SPLLDIV1 160 / 2 = 80Mhz */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_4, /* SPLLDIV2 160 / 4 = 40Mhz */
.prediv = 1, /* PREDIV */
.mult = 40, /* MULT */
.mult = 40, /* MULT 8 / 1 * 40 / 2 = 160Mhz */
.src = 0, /* SOURCE */
.initialize = true, /* Initialize */
.locked = false, /* LK */