From 96e05481b448c0ced3c69af08d60571927731df0 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Tue, 14 Nov 2023 09:33:23 +0100 Subject: [PATCH] ucans32k1: SPLLDIV2 set to 40Mhz --- boards/nxp/ucans32k146/src/clockconfig.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/nxp/ucans32k146/src/clockconfig.c b/boards/nxp/ucans32k146/src/clockconfig.c index b892215aad..2c1abb1263 100644 --- a/boards/nxp/ucans32k146/src/clockconfig.c +++ b/boards/nxp/ucans32k146/src/clockconfig.c @@ -109,10 +109,10 @@ const struct clock_configuration_s g_initial_clkconfig = { .spll = { .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ - .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ - .div2 = SCG_ASYNC_CLOCK_DIV_BY_2, /* SPLLDIV2 */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_2, /* SPLLDIV1 160 / 2 = 80Mhz */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_4, /* SPLLDIV2 160 / 4 = 40Mhz */ .prediv = 1, /* PREDIV */ - .mult = 40, /* MULT */ + .mult = 40, /* MULT 8 / 1 * 40 / 2 = 160Mhz */ .src = 0, /* SOURCE */ .initialize = true, /* Initialize */ .locked = false, /* LK */