forked from Archive/PX4-Autopilot
Switch to the 'normal' way of doing register accessors.
Be more aggressive en/disabling DMA in the UART, since ST say you should.
This commit is contained in:
px4dev
parent
c21237667b
commit
52096f017f
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@ -65,6 +65,8 @@
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#include <systemlib/perf_counter.h>
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#include <modules/px4iofirmware/protocol.h>
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#include "interface.h"
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const unsigned max_rw_regs = 32; // by agreement w/IO
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@ -80,6 +82,16 @@ struct IOPacket {
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};
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#pragma pack(pop)
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/* serial register accessors */
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#define REG(_x) (*(volatile uint32_t *)(PX4IO_SERIAL_BASE + _x))
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#define rSR REG(STM32_USART_SR_OFFSET)
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#define rDR REG(STM32_USART_DR_OFFSET)
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#define rBRR REG(STM32_USART_BRR_OFFSET)
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#define rCR1 REG(STM32_USART_CR1_OFFSET)
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#define rCR2 REG(STM32_USART_CR2_OFFSET)
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#define rCR3 REG(STM32_USART_CR3_OFFSET)
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#define rGTPR REG(STM32_USART_GTPR_OFFSET)
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#define PKT_SIZE(_n) (4 + (2 * (_n)))
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class PX4IO_serial : public PX4IO_interface
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@ -149,28 +161,6 @@ private:
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*/
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void _abort_dma();
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/**
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* Serial register accessors.
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*/
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volatile uint32_t &_sreg(unsigned offset)
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{
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return *(volatile uint32_t *)(PX4IO_SERIAL_BASE + offset);
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}
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uint32_t _SR() { return _sreg(STM32_USART_SR_OFFSET); }
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void _SR(uint32_t val) { _sreg(STM32_USART_SR_OFFSET) = val; }
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uint32_t _DR() { return _sreg(STM32_USART_DR_OFFSET); }
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void _DR(uint32_t val) { _sreg(STM32_USART_DR_OFFSET) = val; }
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uint32_t _BRR() { return _sreg(STM32_USART_BRR_OFFSET); }
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void _BRR(uint32_t val) { _sreg(STM32_USART_BRR_OFFSET) = val; }
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uint32_t _CR1() { return _sreg(STM32_USART_CR1_OFFSET); }
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void _CR1(uint32_t val) { _sreg(STM32_USART_CR1_OFFSET) = val; }
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uint32_t _CR2() { return _sreg(STM32_USART_CR2_OFFSET); }
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void _CR2(uint32_t val) { _sreg(STM32_USART_CR2_OFFSET) = val; }
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uint32_t _CR3() { return _sreg(STM32_USART_CR3_OFFSET); }
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void _CR3(uint32_t val) { _sreg(STM32_USART_CR3_OFFSET) = val; }
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uint32_t _GTPR() { return _sreg(STM32_USART_GTPR_OFFSET); }
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void _GTPR(uint32_t val) { _sreg(STM32_USART_GTPR_OFFSET) = val; }
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/**
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* Performance counters.
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*/
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@ -213,24 +203,28 @@ PX4IO_serial::PX4IO_serial() :
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stm32_configgpio(PX4IO_SERIAL_RX_GPIO);
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/* reset & configure the UART */
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_CR1(0);
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_CR2(0);
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_CR3(0);
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rCR1 = 0;
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rCR2 = 0;
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rCR3 = 0;
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/* eat any existing interrupt status */
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(void)rSR;
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(void)rDR;
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/* configure line speed */
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uint32_t usartdiv32 = PX4IO_SERIAL_CLOCK / (PX4IO_SERIAL_BITRATE / 2);
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uint32_t mantissa = usartdiv32 >> 5;
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uint32_t fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
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_BRR((mantissa << USART_BRR_MANT_SHIFT) | (fraction << USART_BRR_FRAC_SHIFT));
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/* enable UART in DMA mode, enable error and line idle interrupts */
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_CR3(USART_CR3_DMAR | USART_CR3_DMAT | USART_CR3_EIE);
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_CR1(USART_CR1_RE | USART_CR1_TE | USART_CR1_UE | USART_CR1_IDLEIE);
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rBRR = (mantissa << USART_BRR_MANT_SHIFT) | (fraction << USART_BRR_FRAC_SHIFT);
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/* attach serial interrupt handler */
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irq_attach(PX4IO_SERIAL_VECTOR, _interrupt);
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up_enable_irq(PX4IO_SERIAL_VECTOR);
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/* enable UART in DMA mode, enable error and line idle interrupts */
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/* rCR3 = USART_CR3_EIE;*/
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rCR1 = USART_CR1_RE | USART_CR1_TE | USART_CR1_UE /*| USART_CR1_IDLEIE*/;
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/* create semaphores */
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sem_init(&_completion_semaphore, 0, 0);
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sem_init(&_bus_semaphore, 0, 1);
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@ -250,9 +244,9 @@ PX4IO_serial::~PX4IO_serial()
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}
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/* reset the UART */
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_CR1(0);
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_CR2(0);
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_CR3(0);
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rCR1 = 0;
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rCR2 = 0;
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rCR3 = 0;
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/* detach our interrupt handler */
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up_disable_irq(PX4IO_SERIAL_VECTOR);
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@ -292,30 +286,35 @@ PX4IO_serial::test(unsigned mode)
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/* kill DMA, this is a PIO test */
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stm32_dmastop(_tx_dma);
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stm32_dmastop(_rx_dma);
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_CR3(_CR3() & ~(USART_CR3_DMAR | USART_CR3_DMAT));
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rCR3 &= ~(USART_CR3_DMAR | USART_CR3_DMAT);
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for (;;) {
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while (!(_SR() & USART_SR_TXE))
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while (!(rSR & USART_SR_TXE))
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;
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_DR(0x55);
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rDR = 0x55;
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}
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return 0;
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case 1:
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lowsyslog("test 1\n");
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{
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uint16_t value = 0x5555;
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for (unsigned count = 0;; count++) {
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if (set_reg(0x55, 0x55, &value, 1) != OK)
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uint16_t value = count & 0xffff;
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if (set_reg(PX4IO_PAGE_TEST, PX4IO_P_TEST_LED, &value, 1) != OK)
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return -2;
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if (count > 10000) {
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if (count > 100) {
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perf_print_counter(_perf_dmasetup);
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perf_print_counter(_perf_wr);
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count = 0;
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}
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usleep(100000);
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}
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return 0;
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}
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case 2:
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lowsyslog("test 2\n");
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return 0;
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}
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return -1;
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}
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@ -333,6 +332,9 @@ PX4IO_serial::set_reg(uint8_t page, uint8_t offset, const uint16_t *values, unsi
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_dma_buffer.page = page;
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_dma_buffer.offset = offset;
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memcpy((void *)&_dma_buffer.regs[0], (void *)values, (2 * num_values));
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for (unsigned i = num_values; i < max_rw_regs; i++)
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_dma_buffer.regs[i] = 0x55aa;
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/* XXX implement check byte */
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/* start the transaction and wait for it to complete */
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@ -377,6 +379,10 @@ int
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PX4IO_serial::_wait_complete(bool expect_reply, unsigned tx_length)
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{
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/* clear any lingering error status */
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(void)rSR;
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(void)rDR;
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/* start RX DMA */
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if (expect_reply) {
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perf_begin(_perf_rd);
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@ -397,6 +403,7 @@ PX4IO_serial::_wait_complete(bool expect_reply, unsigned tx_length)
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DMA_SCR_PBURST_SINGLE |
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DMA_SCR_MBURST_SINGLE);
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stm32_dmastart(_rx_dma, _dma_callback, this, false);
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rCR3 |= USART_CR3_DMAR;
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perf_end(_perf_dmasetup);
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} else {
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@ -419,6 +426,8 @@ PX4IO_serial::_wait_complete(bool expect_reply, unsigned tx_length)
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DMA_SCR_PBURST_SINGLE |
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DMA_SCR_MBURST_SINGLE);
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stm32_dmastart(_tx_dma, /*expect_reply ? nullptr :*/ _dma_callback, this, false);
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rCR3 |= USART_CR3_DMAT;
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perf_end(_perf_dmasetup);
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/* compute the deadline for a 5ms timeout */
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@ -439,8 +448,18 @@ PX4IO_serial::_wait_complete(bool expect_reply, unsigned tx_length)
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for (;;) {
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ret = sem_timedwait(&_completion_semaphore, &abstime);
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if (ret == OK)
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if (ret == OK) {
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/* check for DMA errors */
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if (_tx_dma_status & DMA_STATUS_TEIF) {
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lowsyslog("DMA transmit error\n");
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ret = -1;
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}
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if (_rx_dma_status & DMA_STATUS_TEIF) {
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lowsyslog("DMA receive error\n");
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ret = -1;
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}
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break;
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}
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if (errno == ETIMEDOUT) {
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lowsyslog("timeout waiting for PX4IO link (%d/%d)\n", stm32_dmaresidual(_tx_dma), stm32_dmaresidual(_rx_dma));
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@ -452,24 +471,14 @@ PX4IO_serial::_wait_complete(bool expect_reply, unsigned tx_length)
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lowsyslog("unexpected ret %d/%d\n", ret, errno);
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}
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/* check for DMA errors */
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if (ret == OK) {
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if (_tx_dma_status & DMA_STATUS_TEIF) {
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lowsyslog("DMA transmit error\n");
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ret = -1;
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}
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if (_rx_dma_status & DMA_STATUS_TEIF) {
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lowsyslog("DMA receive error\n");
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ret = -1;
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}
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perf_count(_perf_errors);
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}
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/* reset DMA status */
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_tx_dma_status = _dma_status_inactive;
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_rx_dma_status = _dma_status_inactive;
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/* update counters */
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perf_end(expect_reply ? _perf_rd : _perf_wr);
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if (ret != OK)
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perf_count(_perf_errors);
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return ret;
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}
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@ -497,6 +506,9 @@ PX4IO_serial::_do_tx_dma_callback(unsigned status)
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/* save TX status */
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_tx_dma_status = status;
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/* disable UART DMA */
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rCR3 &= ~USART_CR3_DMAT;
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/* if we aren't going on to expect a reply, complete now */
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if (_rx_dma_status != _dma_status_waiting)
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sem_post(&_completion_semaphore);
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@ -512,14 +524,18 @@ PX4IO_serial::_do_rx_dma_callback(unsigned status)
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if (_rx_dma_status == _dma_status_waiting) {
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/* check for packet overrun - this will occur after DMA completes */
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if (_SR() & (USART_SR_ORE | USART_SR_RXNE)) {
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_DR();
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uint32_t sr = rSR;
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if (sr & (USART_SR_ORE | USART_SR_RXNE)) {
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(void)rDR;
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status = DMA_STATUS_TEIF;
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}
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/* save RX status */
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_rx_dma_status = status;
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/* disable UART DMA */
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rCR3 &= ~USART_CR3_DMAR;
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/* DMA may have stopped short */
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_rx_length = sizeof(IOPacket) - stm32_dmaresidual(_rx_dma);
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@ -539,12 +555,12 @@ PX4IO_serial::_interrupt(int irq, void *context)
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void
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PX4IO_serial::_do_interrupt()
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{
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uint32_t sr = _SR(); /* get UART status register */
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uint32_t sr = rSR; /* get UART status register */
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/* handle error/exception conditions */
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if (sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_IDLE)) {
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/* read DR to clear status */
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_DR();
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(void)rDR;
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} else {
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ASSERT(0);
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}
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@ -593,8 +609,17 @@ PX4IO_serial::_do_interrupt()
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void
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PX4IO_serial::_abort_dma()
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{
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/* disable UART DMA */
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rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR);
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(void)rSR;
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(void)rDR;
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(void)rDR;
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/* stop DMA */
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stm32_dmastop(_tx_dma);
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stm32_dmastop(_rx_dma);
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/* complete DMA as though in error */
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_do_tx_dma_callback(DMA_STATUS_TEIF);
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_do_rx_dma_callback(DMA_STATUS_TEIF);
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