mirror of https://github.com/ArduPilot/ardupilot
345 lines
10 KiB
C
345 lines
10 KiB
C
/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Modified for use in AP_HAL by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#include "hal.h"
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#include "usbcfg.h"
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#include "stm32_util.h"
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#include "watchdog.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief STM32 GPIO static initialization data.
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*/
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#if defined(STM32F100_MCUCONF) || defined(STM32F103_MCUCONF) || defined(STM32F105_MCUCONF)
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const PALConfig pal_default_config =
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{
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{VAL_GPIOA_ODR, VAL_GPIOA_CRL, VAL_GPIOA_CRH},
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{VAL_GPIOB_ODR, VAL_GPIOB_CRL, VAL_GPIOB_CRH},
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{VAL_GPIOC_ODR, VAL_GPIOC_CRL, VAL_GPIOC_CRH},
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{VAL_GPIOD_ODR, VAL_GPIOD_CRL, VAL_GPIOD_CRH},
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{VAL_GPIOE_ODR, VAL_GPIOE_CRL, VAL_GPIOE_CRH},
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};
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#else //Other than STM32F1/F3 series
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/**
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* @brief Type of STM32 GPIO port setup.
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*/
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typedef struct {
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uint32_t moder;
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uint32_t otyper;
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uint32_t ospeedr;
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uint32_t pupdr;
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uint32_t odr;
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uint32_t afrl;
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uint32_t afrh;
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} gpio_setup_t;
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/**
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* @brief Type of STM32 GPIO initialization data.
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*/
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typedef struct {
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#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
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gpio_setup_t PAData;
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#endif
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#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
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gpio_setup_t PBData;
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#endif
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#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
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gpio_setup_t PCData;
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#endif
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#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
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gpio_setup_t PDData;
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#endif
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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gpio_setup_t PEData;
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#endif
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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gpio_setup_t PFData;
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#endif
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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gpio_setup_t PGData;
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#endif
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#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
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gpio_setup_t PHData;
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#endif
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#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
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gpio_setup_t PIData;
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#endif
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#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
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gpio_setup_t PJData;
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#endif
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#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
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gpio_setup_t PKData;
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#endif
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} gpio_config_t;
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/**
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* @brief STM32 GPIO static initialization data.
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*/
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static const gpio_config_t gpio_default_config = {
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#if STM32_HAS_GPIOA
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
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#endif
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#if STM32_HAS_GPIOB
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
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#endif
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#if STM32_HAS_GPIOC
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
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#endif
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#if STM32_HAS_GPIOD
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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#endif
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#if STM32_HAS_GPIOE
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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#endif
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#if STM32_HAS_GPIOF
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
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#endif
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#if STM32_HAS_GPIOG
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
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#endif
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#if STM32_HAS_GPIOH
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
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#endif
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#if STM32_HAS_GPIOI
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
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#endif
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#if STM32_HAS_GPIOJ
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{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
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VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
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#endif
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#if STM32_HAS_GPIOK
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{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
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VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
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#endif
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
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gpiop->OTYPER = config->otyper;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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gpiop->AFRL = config->afrl;
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gpiop->AFRH = config->afrh;
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gpiop->MODER = config->moder;
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}
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static void stm32_gpio_init(void) {
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/* Enabling GPIO-related clocks, the mask comes from the
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registry header file.*/
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#if defined(STM32H7)
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#if !EXT_FLASH_SIZE_MB // if we have external flash resetting GPIO might disable all comms with it
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rccResetAHB4(STM32_GPIO_EN_MASK);
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#endif
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rccEnableAHB4(STM32_GPIO_EN_MASK, true);
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#elif defined(STM32F3)
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rccResetAHB(STM32_GPIO_EN_MASK);
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rccEnableAHB(STM32_GPIO_EN_MASK, true);
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#elif defined(STM32G4) || defined(STM32L4) || defined(STM32L4PLUS)
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rccResetAHB2(STM32_GPIO_EN_MASK);
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rccEnableAHB2(STM32_GPIO_EN_MASK, true);
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#else
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rccResetAHB1(STM32_GPIO_EN_MASK);
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rccEnableAHB1(STM32_GPIO_EN_MASK, true);
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#endif
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/* Initializing all the defined GPIO ports.*/
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#if STM32_HAS_GPIOA
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gpio_init(GPIOA, &gpio_default_config.PAData);
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#endif
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#if STM32_HAS_GPIOB
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gpio_init(GPIOB, &gpio_default_config.PBData);
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#endif
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#if STM32_HAS_GPIOC
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gpio_init(GPIOC, &gpio_default_config.PCData);
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#endif
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#if STM32_HAS_GPIOD
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gpio_init(GPIOD, &gpio_default_config.PDData);
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#endif
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#if STM32_HAS_GPIOE
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gpio_init(GPIOE, &gpio_default_config.PEData);
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#endif
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#if STM32_HAS_GPIOF
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gpio_init(GPIOF, &gpio_default_config.PFData);
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#endif
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#if STM32_HAS_GPIOG
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gpio_init(GPIOG, &gpio_default_config.PGData);
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#endif
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#if STM32_HAS_GPIOH
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gpio_init(GPIOH, &gpio_default_config.PHData);
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#endif
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#if STM32_HAS_GPIOI
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gpio_init(GPIOI, &gpio_default_config.PIData);
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#endif
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#if STM32_HAS_GPIOJ
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gpio_init(GPIOJ, &gpio_default_config.PJData);
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#endif
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#if STM32_HAS_GPIOK
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gpio_init(GPIOK, &gpio_default_config.PKData);
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#endif
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}
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#endif //!STM32F100_MCUCONF
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/**
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* @brief Early initialization code.
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* @details This initialization must be performed just after stack setup
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* and before any other initialization.
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*
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* You must not rely on: 1) BSS variables being cleared 2) DATA Variables being initialized 3) RAM functions to be in RAM
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* You can rely on: 1) const variables or tables 2) flash code 3) automatic variables
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*/
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void __early_init(void) {
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#if !defined(STM32F1)
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stm32_gpio_init();
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#endif
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#if !HAL_XIP_ENABLED || defined(HAL_FORCE_CLOCK_INIT)
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// if running from external flash then the clocks must not be reset - instead rely on the bootloader to setup
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stm32_clock_init();
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#endif
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#if defined(HAL_DISABLE_DCACHE)
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SCB_DisableDCache();
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#endif
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#if defined(STM32H7)
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// ensure ITCM and DTCM are enabled. These could be disabled by the px4
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// bootloader
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SCB->ITCMCR |= 1; // ITCM enable
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SCB->DTCMCR |= 1; // DTCM enable
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#ifdef STM32_NOCACHE_MPU_REGION_1
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// disable cache on configured regions so they can be used for DMA
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// this requires some coordination with the memory map in the MCU configuration script
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mpuConfigureRegion(STM32_NOCACHE_MPU_REGION_1,
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STM32_NOCACHE_MPU_REGION_1_BASE,
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MPU_RASR_ATTR_AP_RW_RW |
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MPU_RASR_ATTR_NON_CACHEABLE |
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STM32_NOCACHE_MPU_REGION_1_SIZE |
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MPU_RASR_ENABLE);
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#endif
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#ifdef STM32_NOCACHE_MPU_REGION_2
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mpuConfigureRegion(STM32_NOCACHE_MPU_REGION_2,
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STM32_NOCACHE_MPU_REGION_2_BASE,
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MPU_RASR_ATTR_AP_RW_RW |
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MPU_RASR_ATTR_NON_CACHEABLE |
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STM32_NOCACHE_MPU_REGION_2_SIZE |
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MPU_RASR_ENABLE);
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#endif
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#endif
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}
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void __late_init(void) {
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halInit();
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chSysInit();
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/*
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* Initialize RNG
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*/
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#if HAL_USE_HW_RNG && defined(RNG)
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rccEnableAHB2(RCC_AHB2ENR_RNGEN, 0);
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RNG->CR |= RNG_CR_IE;
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RNG->CR |= RNG_CR_RNGEN;
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#endif
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stm32_watchdog_save_reason();
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#ifndef HAL_BOOTLOADER_BUILD
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stm32_watchdog_clear_reason();
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#endif
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#if CH_CFG_USE_HEAP == TRUE
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malloc_init();
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#endif
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#ifdef HAL_USB_PRODUCT_ID
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setup_usb_strings();
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#endif
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}
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#if HAL_USE_SDC || defined(__DOXYGEN__)
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/**
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* @brief SDC card detection.
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*/
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bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
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(void)sdcp;
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return true;
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}
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/**
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* @brief SDC card write protection detection.
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*/
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bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
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(void)sdcp;
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return false;
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}
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#endif /* HAL_USE_SDC */
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#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
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/**
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* @brief MMC_SPI card detection.
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*/
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bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
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(void)mmcp;
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/* TODO: Fill the implementation.*/
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return true;
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}
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/**
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* @brief MMC_SPI card write protection detection.
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*/
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bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
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(void)mmcp;
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/* TODO: Fill the implementation.*/
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return false;
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}
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#endif
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/**
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* @brief Board-specific initialization code.
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* @todo Add your board-specific code, if any.
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*/
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void boardInit(void) {
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HAL_BOARD_INIT_HOOK_CALL
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}
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