mirror of https://github.com/ArduPilot/ardupilot
608 lines
22 KiB
C
608 lines
22 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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this header is modelled on the one for the Nucleo-144 H743 board from ChibiOS
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*/
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#pragma once
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// we want to cope with both revision XY chips and newer chips
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#define STM32_ENFORCE_H7_REV_XY
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#ifndef STM32_LSECLK
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#define STM32_LSECLK 32768U
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#endif
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#ifndef STM32_LSEDRV
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#define STM32_LSEDRV (3U << 3U)
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#endif
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/*
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* STM32H7xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32H7xx_MCUCONF
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#define STM32H742_MCUCONF
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#define STM32H743_MCUCONF
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#define STM32H753_MCUCONF
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#define STM32H745_MCUCONF
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#define STM32H750_MCUCONF
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#define STM32H755_MCUCONF
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#define STM32H747_MCUCONF
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#define STM32H757_MCUCONF
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/*
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* General settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_TARGET_CORE 1
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/*
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* Memory attributes settings.
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*/
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#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
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#define STM32_NOCACHE_SRAM1_SRAM2 FALSE
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#define STM32_NOCACHE_SRAM3 FALSE
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/*
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* PWR system settings.
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* Reading STM32 Reference Manual is required, settings in PWR_CR3 are
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* very critical.
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* Register constants are taken from the ST header.
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*/
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#define STM32_VOS STM32_VOS_SCALE1
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#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
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#define STM32_PWR_CR2 (PWR_CR2_BREN)
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#ifdef SMPS_PWR
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#define STM32_PWR_CR3 (PWR_CR3_SMPSEN | PWR_CR3_USB33DEN)
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#else
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#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
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#endif
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#define STM32_PWR_CPUCR 0
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/*
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* Clock tree static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_LSI_ENABLED FALSE
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#define STM32_CSI_ENABLED FALSE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_HSIDIV STM32_HSIDIV_DIV1
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/*
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setup PLLs based on HSE clock
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*/
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#if STM32_HSECLK == 0U
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// no crystal, this gives 400MHz system clock
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#define STM32_HSE_ENABLED FALSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_PLL1_DIVM_VALUE 4
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#define STM32_PLL2_DIVM_VALUE 8
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#define STM32_PLL3_DIVM_VALUE 4
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#define STM32_PLLSRC STM32_PLLSRC_HSI_CK
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
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#define STM32_CKPERSEL STM32_CKPERSEL_HSI_CK
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#elif STM32_HSECLK == 8000000U
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// this gives 400MHz system clock
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSI_ENABLED FALSE
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#define STM32_PLL1_DIVM_VALUE 1
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#define STM32_PLL2_DIVM_VALUE 1
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#define STM32_PLL3_DIVM_VALUE 2
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#elif STM32_HSECLK == 16000000U
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// this gives 400MHz system clock
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSI_ENABLED FALSE
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#define STM32_PLL1_DIVM_VALUE 2
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#define STM32_PLL2_DIVM_VALUE 2
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#define STM32_PLL3_DIVM_VALUE 4
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#elif STM32_HSECLK == 24000000U
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// this gives 400MHz system clock
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSI_ENABLED FALSE
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#define STM32_PLL1_DIVM_VALUE 3
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#define STM32_PLL2_DIVM_VALUE 2
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#define STM32_PLL3_DIVM_VALUE 6
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#elif STM32_HSECLK == 25000000U
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// this gives 400MHz system clock
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#define STM32_HSE_ENABLED TRUE
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#define STM32_HSI_ENABLED FALSE
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#define STM32_PLL1_DIVM_VALUE 2
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#define STM32_PLL2_DIVM_VALUE 5
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#define STM32_PLL3_DIVM_VALUE 5
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#else
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#error "Unsupported HSE clock"
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#endif
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#if STM32_HSECLK == 0U
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// no crystal
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#define STM32_PLL1_DIVN_VALUE 50
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 8
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#define STM32_PLL1_DIVR_VALUE 2
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#define STM32_PLL2_DIVN_VALUE 45
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#define STM32_PLL2_DIVP_VALUE 2
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#define STM32_PLL2_DIVQ_VALUE 5
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#define STM32_PLL2_DIVR_VALUE 1
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#define STM32_PLL3_DIVN_VALUE 15
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#define STM32_PLL3_DIVP_VALUE 3
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#define STM32_PLL3_DIVQ_VALUE 5
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#define STM32_PLL3_DIVR_VALUE 8
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#elif (STM32_HSECLK == 8000000U) || (STM32_HSECLK == 16000000U)
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// common clock tree for multiples of 8MHz crystals
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#define STM32_PLL1_DIVN_VALUE 100
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 8
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#define STM32_PLL1_DIVR_VALUE 2
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#define STM32_PLL2_DIVN_VALUE 45
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#define STM32_PLL2_DIVP_VALUE 2
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#define STM32_PLL2_DIVQ_VALUE 5
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#define STM32_PLL2_DIVR_VALUE 1
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#define STM32_PLL3_DIVN_VALUE 72
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#define STM32_PLL3_DIVP_VALUE 3
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#define STM32_PLL3_DIVQ_VALUE 6
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#define STM32_PLL3_DIVR_VALUE 9
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#elif STM32_HSECLK == 24000000U
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#define STM32_PLL1_DIVN_VALUE 100
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 8
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#define STM32_PLL1_DIVR_VALUE 2
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#define STM32_PLL2_DIVN_VALUE 30
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#define STM32_PLL2_DIVP_VALUE 2
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#define STM32_PLL2_DIVQ_VALUE 5
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#define STM32_PLL2_DIVR_VALUE 1
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#define STM32_PLL3_DIVN_VALUE 72
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#define STM32_PLL3_DIVP_VALUE 3
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#define STM32_PLL3_DIVQ_VALUE 6
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#define STM32_PLL3_DIVR_VALUE 9
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#elif STM32_HSECLK == 25000000U
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#define STM32_PLL1_DIVN_VALUE 64
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 8
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#define STM32_PLL1_DIVR_VALUE 2
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#define STM32_PLL2_DIVN_VALUE 72
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#define STM32_PLL2_DIVP_VALUE 2
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#define STM32_PLL2_DIVQ_VALUE 5
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#define STM32_PLL2_DIVR_VALUE 1
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#define STM32_PLL3_DIVN_VALUE 48
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#define STM32_PLL3_DIVP_VALUE 3
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#define STM32_PLL3_DIVQ_VALUE 5
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#define STM32_PLL3_DIVR_VALUE 8
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#endif // clock selection
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/*
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* PLLs static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#ifndef STM32_PLLSRC
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#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
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#endif
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#define STM32_PLLCFGR_MASK ~0
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#define STM32_PLL1_ENABLED TRUE
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#define STM32_PLL1_P_ENABLED TRUE
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#define STM32_PLL1_Q_ENABLED TRUE
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#define STM32_PLL1_R_ENABLED TRUE
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#define STM32_PLL1_FRACN_VALUE 0
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#define STM32_PLL2_ENABLED TRUE
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#define STM32_PLL2_P_ENABLED TRUE
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#define STM32_PLL2_Q_ENABLED TRUE
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#define STM32_PLL2_R_ENABLED TRUE
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#define STM32_PLL2_FRACN_VALUE 0
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#define STM32_PLL3_ENABLED TRUE
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#define STM32_PLL3_P_ENABLED TRUE
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#define STM32_PLL3_Q_ENABLED TRUE
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#define STM32_PLL3_R_ENABLED TRUE
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#define STM32_PLL3_FRACN_VALUE 0
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/*
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* Core clocks dynamic settings (can be changed at runtime).
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_SW STM32_SW_PLL1_P_CK
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#define STM32_RTCSEL STM32_RTCSEL_NOCLK
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#define STM32_D1CPRE STM32_D1CPRE_DIV1
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#define STM32_D1HPRE STM32_D1HPRE_DIV2
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#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
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#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
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#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
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#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
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/*
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* Peripherals clocks static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#ifndef STM32_MCO1SEL
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#define STM32_MCO1SEL STM32_MCO1SEL_HSE_CK
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#endif
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#define STM32_MCO1PRE_VALUE 4
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#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
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#define STM32_MCO2PRE_VALUE 4
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#define STM32_TIMPRE_ENABLE TRUE
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#define STM32_HRTIMSEL 0
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#define STM32_STOPKERWUCK 0
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#define STM32_STOPWUCK 0
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#define STM32_RTCPRE_VALUE 8
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#ifndef STM32_CKPERSEL
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#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
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#endif
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
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#define STM32_QSPISEL STM32_QSPISEL_PLL2_R_CK
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#define STM32_FMCSEL STM32_QSPISEL_HCLK
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#define STM32_SWPSEL STM32_SWPSEL_PCLK1
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#define STM32_FDCANSEL STM32_FDCANSEL_PLL2_Q_CK
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#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
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#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
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#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
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#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
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#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
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#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_CECSEL STM32_CECSEL_DISABLE
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#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
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#define STM32_I2C123SEL STM32_I2C123SEL_PLL3_R_CK
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#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
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#define STM32_USART16SEL STM32_USART16SEL_PCLK2
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#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
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#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
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#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
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#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
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#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK
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#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
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#define STM32_I2C4SEL STM32_I2C4SEL_PLL3_R_CK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 15
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_21_PRIORITY 6
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#define STM32_IRQ_FDCAN1_PRIORITY 10
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#define STM32_IRQ_FDCAN2_PRIORITY 10
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#define STM32_IRQ_MDMA_PRIORITY 9
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#define STM32_IRQ_QUADSPI1_PRIORITY 10
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#define STM32_IRQ_SDMMC1_PRIORITY 9
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#define STM32_IRQ_SDMMC2_PRIORITY 9
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#define STM32_IRQ_TIM1_UP_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_TIM6_PRIORITY 7
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#define STM32_IRQ_TIM7_PRIORITY 7
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#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
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#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
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#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
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#define STM32_IRQ_TIM8_CC_PRIORITY 7
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#define STM32_IRQ_TIM15_PRIORITY 7
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#define STM32_IRQ_TIM16_PRIORITY 7
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#define STM32_IRQ_TIM17_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART3_PRIORITY 12
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#define STM32_IRQ_UART4_PRIORITY 12
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#define STM32_IRQ_UART5_PRIORITY 12
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#define STM32_IRQ_USART6_PRIORITY 12
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#define STM32_IRQ_UART7_PRIORITY 12
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#define STM32_IRQ_UART8_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_DUAL_MODE FALSE
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_USE_ADC12 TRUE
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#ifndef STM32H750xx
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#define STM32_ADC_USE_ADC3 TRUE
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#endif
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#define STM32_ADC_ADC12_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC3_IRQ_PRIORITY 5
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK
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// we call it ADC1 in hwdef.dat, but driver uses ADC12 for DMA stream
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#define STM32_ADC_ADC12_DMA_STREAM STM32_ADC_ADC1_DMA_STREAM
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_FDCAN1 FALSE
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#define STM32_CAN_USE_FDCAN2 FALSE
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 FALSE
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#define STM32_DAC_USE_DAC1_CH2 FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 FALSE
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#define STM32_GPT_USE_TIM7 FALSE
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#define STM32_GPT_USE_TIM8 FALSE
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#define STM32_GPT_USE_TIM12 FALSE
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#define STM32_GPT_USE_TIM13 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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#define STM32_GPT_USE_TIM15 FALSE
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#define STM32_GPT_USE_TIM16 FALSE
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#define STM32_GPT_USE_TIM17 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C4_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_I2C4_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY 7
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#define STM32_ICU_TIM2_IRQ_PRIORITY 7
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#define STM32_ICU_TIM3_IRQ_PRIORITY 7
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#define STM32_ICU_TIM4_IRQ_PRIORITY 7
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#define STM32_ICU_TIM5_IRQ_PRIORITY 7
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#define STM32_ICU_TIM8_IRQ_PRIORITY 7
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#define STM32_ICU_TIM9_IRQ_PRIORITY 7
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/*
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* MAC driver system settings.
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*/
|
|
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
|
#define STM32_MAC_RECEIVE_BUFFERS 4
|
|
#define STM32_MAC_BUFFERS_SIZE 1522
|
|
#define STM32_MAC_PHY_TIMEOUT 100
|
|
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
|
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
|
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
|
|
|
/*
|
|
* PWM driver system settings.
|
|
*/
|
|
|
|
/*
|
|
* RTC driver system settings.
|
|
*/
|
|
#define STM32_RTC_PRESA_VALUE 32
|
|
#define STM32_RTC_PRESS_VALUE 1024
|
|
#define STM32_RTC_CR_INIT 0
|
|
#define STM32_RTC_TAMPCR_INIT 0
|
|
|
|
/*
|
|
* SDC driver system settings.
|
|
*/
|
|
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
|
|
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000
|
|
#define STM32_SDC_SDMMC_READ_TIMEOUT 1000
|
|
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
|
|
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
|
|
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
|
|
|
|
/*
|
|
* SERIAL driver system settings.
|
|
*/
|
|
#define STM32_SERIAL_USART1_PRIORITY 12
|
|
#define STM32_SERIAL_USART2_PRIORITY 12
|
|
#define STM32_SERIAL_USART3_PRIORITY 12
|
|
#define STM32_SERIAL_UART4_PRIORITY 12
|
|
#define STM32_SERIAL_UART5_PRIORITY 12
|
|
#define STM32_SERIAL_USART6_PRIORITY 12
|
|
#define STM32_SERIAL_UART7_PRIORITY 12
|
|
#define STM32_SERIAL_UART8_PRIORITY 12
|
|
|
|
#define STM32_UART1CLK STM32_PCLK1
|
|
#define STM32_UART2CLK STM32_PCLK1
|
|
#define STM32_UART3CLK STM32_PCLK1
|
|
#define STM32_UART4CLK STM32_PCLK1
|
|
#define STM32_UART5CLK STM32_PCLK1
|
|
#define STM32_UART6CLK STM32_PCLK1
|
|
#define STM32_UART7CLK STM32_PCLK1
|
|
#define STM32_UART8CLK STM32_PCLK1
|
|
|
|
/*
|
|
* SPI driver system settings.
|
|
*/
|
|
#ifndef STM32_SPI_USE_SPI1
|
|
#define STM32_SPI_USE_SPI1 FALSE
|
|
#endif
|
|
#ifndef STM32_SPI_USE_SPI2
|
|
#define STM32_SPI_USE_SPI2 FALSE
|
|
#endif
|
|
#ifndef STM32_SPI_USE_SPI3
|
|
#define STM32_SPI_USE_SPI3 FALSE
|
|
#endif
|
|
#ifndef STM32_SPI_USE_SPI4
|
|
#define STM32_SPI_USE_SPI4 FALSE
|
|
#endif
|
|
#ifndef STM32_SPI_USE_SPI5
|
|
#define STM32_SPI_USE_SPI5 FALSE
|
|
#endif
|
|
#ifndef STM32_SPI_USE_SPI6
|
|
#define STM32_SPI_USE_SPI6 FALSE
|
|
#endif
|
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
|
#define STM32_SPI_SPI4_DMA_PRIORITY 1
|
|
#define STM32_SPI_SPI5_DMA_PRIORITY 1
|
|
#define STM32_SPI_SPI6_DMA_PRIORITY 1
|
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
|
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
|
|
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
|
|
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
|
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
|
|
|
/*
|
|
* ST driver system settings.
|
|
*/
|
|
#define STM32_ST_IRQ_PRIORITY 8
|
|
#ifndef STM32_ST_USE_TIMER
|
|
#define STM32_ST_USE_TIMER 5
|
|
#endif
|
|
|
|
/*
|
|
* UART driver system settings.
|
|
*/
|
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
|
#define STM32_UART_UART7_DMA_PRIORITY 0
|
|
#define STM32_UART_UART8_DMA_PRIORITY 0
|
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
|
|
|
#define STM32_IRQ_LPUART1_PRIORITY 12
|
|
|
|
/*
|
|
* USB driver system settings.
|
|
*/
|
|
#define STM32_USB_USE_OTG1 TRUE
|
|
#define STM32_USB_USE_OTG2 TRUE
|
|
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
|
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
|
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
|
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
|
#define STM32_USB_HOST_WAKEUP_DURATION 2
|
|
|
|
/*
|
|
* WDG driver system settings.
|
|
*/
|
|
#define STM32_WDG_USE_IWDG FALSE
|
|
|
|
#define STM32_EXTI_ENHANCED
|
|
|
|
// limit ISR count per byte
|
|
#define STM32_I2C_ISR_LIMIT 6
|
|
|
|
// limit SDMMC clock to 12.5MHz by default. This increases
|
|
// reliability
|
|
#ifndef STM32_SDC_MAX_CLOCK
|
|
#define STM32_SDC_MAX_CLOCK 12500000
|
|
#endif
|
|
|
|
#ifndef STM32_WSPI_USE_QUADSPI1
|
|
#define STM32_WSPI_USE_QUADSPI1 FALSE
|
|
#endif
|
|
|
|
#if STM32_WSPI_USE_QUADSPI1
|
|
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
|
|
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
|
|
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ((STM32_QSPICLK / HAL_QSPI1_CLK) - 1)
|
|
#endif
|
|
|
|
/*
|
|
we use a fixed allocation of BDMA streams. We previously dynamically
|
|
allocated these, but bugs in the chip make that unreliable. This is
|
|
a tested set of allocations that is known to work on boards that are
|
|
using all 3 of ADC3, I2C4 and SPI6. They are the only peripherals
|
|
that can use BDMA, so fixed allocation is possible as we have 8
|
|
streams and a maximum of 6 needed.
|
|
|
|
The layout is chosen to:
|
|
|
|
- avoid stream 0, as this doesn't work on ADC3 or SPI6_RX for no known reason
|
|
- leave a gap between the peripheral types, as we have previously found that we sometimes
|
|
lost SPI6 BDMA completion interrupts if SPI6 and I2c4 are neighbours
|
|
*/
|
|
#define STM32_I2C_I2C4_RX_BDMA_STREAM 1
|
|
#define STM32_I2C_I2C4_TX_BDMA_STREAM 2
|
|
#define STM32_SPI_SPI6_RX_BDMA_STREAM 4
|
|
#define STM32_SPI_SPI6_TX_BDMA_STREAM 5
|
|
#define STM32_ADC_ADC3_BDMA_STREAM 7
|
|
|