mirror of https://github.com/ArduPilot/ardupilot
220 lines
6.5 KiB
C++
220 lines
6.5 KiB
C++
/*
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driver for RAMTRON FRAM persistent memory devices. These are used
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for parameter and waypoint storage on most FMUv1, FMUv2, FMUv3 and FMUv4
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boards
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*/
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#include "AP_RAMTRON.h"
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#include <AP_Math/crc.h>
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#include <AP_Math/AP_Math.h>
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extern const AP_HAL::HAL &hal;
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// register numbers
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static const uint8_t RAMTRON_RDID = 0x9f;
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static const uint8_t RAMTRON_READ = 0x03;
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static const uint8_t RAMTRON_WREN = 0x06;
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static const uint8_t RAMTRON_WRITE = 0x02;
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#define RAMTRON_RETRIES 10
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#define RAMTRON_DELAY_MS 10
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/*
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list of supported devices. Thanks to NuttX ramtron driver
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*/
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const AP_RAMTRON::ramtron_id AP_RAMTRON::ramtron_ids[] = {
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{ 0x21, 0x00, 16, 2, RDID_type::Cypress }, // FM25V01
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{ 0x21, 0x08, 16, 2, RDID_type::Cypress }, // FM25V01A
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{ 0x22, 0x00, 32, 2, RDID_type::Cypress }, // FM25V02
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{ 0x22, 0x08, 32, 2, RDID_type::Cypress }, // FM25V02A
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{ 0x22, 0x48, 32, 2, RDID_type::Cypress }, // FM25V02A - Extended Temperature Version
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{ 0x22, 0x01, 32, 2, RDID_type::Cypress }, // FM25VN02
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{ 0x23, 0x00, 64, 2, RDID_type::Cypress }, // FM25V05
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{ 0x23, 0x01, 64, 2, RDID_type::Cypress }, // FM25VN05
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{ 0x24, 0x00, 128, 3, RDID_type::Cypress }, // FM25V10
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{ 0x24, 0x01, 128, 3, RDID_type::Cypress }, // FM25VN10
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{ 0x25, 0x08, 256, 3, RDID_type::Cypress }, // FM25V20A
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{ 0x26, 0x08, 512, 3, RDID_type::Cypress }, // CY15B104Q
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{ 0x27, 0x03, 128, 3, RDID_type::Fujitsu }, // MB85RS1MT
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{ 0x05, 0x09, 32, 2, RDID_type::Fujitsu }, // MB85RS256B
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{ 0x24, 0x03, 16, 2, RDID_type::Fujitsu }, // MB85RS128TY
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};
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// initialise the driver
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bool AP_RAMTRON::init(void)
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{
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dev = hal.spi->get_device("ramtron");
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if (!dev) {
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DEV_PRINTF("No RAMTRON device\n");
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return false;
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}
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WITH_SEMAPHORE(dev->get_semaphore());
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struct cypress_rdid {
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uint8_t manufacturer[6];
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uint8_t memory;
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uint8_t id1;
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uint8_t id2;
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};
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struct fujitsu_rdid {
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uint8_t manufacturer[2];
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uint8_t id1;
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uint8_t id2;
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};
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uint8_t rdid[sizeof(cypress_rdid)];
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if (!dev->read_registers(RAMTRON_RDID, rdid, sizeof(rdid))) {
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return false;
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}
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for (uint8_t i = 0; i < ARRAY_SIZE(ramtron_ids); i++) {
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if (ramtron_ids[i].rdid_type == RDID_type::Cypress) {
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const cypress_rdid *cypress = (const cypress_rdid *)rdid;
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if (ramtron_ids[i].id1 == cypress->id1 &&
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ramtron_ids[i].id2 == cypress->id2) {
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id = i;
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break;
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}
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} else if (ramtron_ids[i].rdid_type == RDID_type::Fujitsu) {
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const fujitsu_rdid *fujitsu = (const fujitsu_rdid *)rdid;
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if (ramtron_ids[i].id1 == fujitsu->id1 &&
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ramtron_ids[i].id2 == fujitsu->id2) {
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id = i;
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break;
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}
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}
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}
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if (id == UINT8_MAX) {
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DEV_PRINTF("Unknown RAMTRON device\n");
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return false;
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}
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return true;
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}
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/*
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send a command and offset
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*/
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void AP_RAMTRON::send_offset(uint8_t cmd, uint32_t offset) const
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{
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if (ramtron_ids[id].addrlen == 3) {
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uint8_t b[4] = { cmd, uint8_t((offset>>16)&0xFF), uint8_t((offset>>8)&0xFF), uint8_t(offset&0xFF) };
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dev->transfer(b, sizeof(b), nullptr, 0);
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} else /* len 2 */ {
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uint8_t b[3] = { cmd, uint8_t((offset>>8)&0xFF), uint8_t(offset&0xFF) };
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dev->transfer(b, sizeof(b), nullptr, 0);
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}
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}
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// read from device
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bool AP_RAMTRON::read(uint32_t offset, uint8_t *buf, uint32_t size)
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{
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// Don't allow reads outside of the FRAM memory.
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// NOTE: The FRAM devices will wrap back to address 0x0000 if they read past
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// the end of their internal memory, so while we'll get data back, it won't
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// be what we expect.
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if ((size > get_size()) ||
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(offset > (get_size() - size))) {
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return false;
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}
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const uint8_t maxread = 128;
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while (size > maxread) {
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if (!read(offset, buf, maxread)) {
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return false;
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}
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offset += maxread;
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buf += maxread;
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size -= maxread;
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}
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for (uint8_t r=0; r<RAMTRON_RETRIES; r++) {
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if (r != 0) {
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hal.scheduler->delay(RAMTRON_DELAY_MS);
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}
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/*
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transfer each block twice and compare with a crc. This is to
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prevent transient errors from causing parameter corruption
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*/
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{
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WITH_SEMAPHORE(dev->get_semaphore());
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dev->set_chip_select(true);
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send_offset(RAMTRON_READ, offset);
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dev->transfer(nullptr, 0, buf, size);
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dev->set_chip_select(false);
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}
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uint32_t crc1 = crc_crc32(0, buf, size);
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{
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WITH_SEMAPHORE(dev->get_semaphore());
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dev->set_chip_select(true);
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send_offset(RAMTRON_READ, offset);
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dev->transfer(nullptr, 0, buf, size);
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dev->set_chip_select(false);
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}
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uint32_t crc2 = crc_crc32(0, buf, size);
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if (crc1 == crc2) {
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// all good
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return true;
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}
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}
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return false;
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}
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// write to device
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bool AP_RAMTRON::write(uint32_t offset, const uint8_t *buf, uint32_t size)
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{
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// Don't allow writes outside of the FRAM memory.
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// NOTE: The FRAM devices will wrap back to address 0x0000 if they write past
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// the end of their internal memory, so we could accidentally overwrite the
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// wrong memory location.
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if ((size > get_size()) ||
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(offset > (get_size() - size))) {
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return false;
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}
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WITH_SEMAPHORE(dev->get_semaphore());
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for (uint8_t r=0; r<RAMTRON_RETRIES; r++) {
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if (r != 0) {
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hal.scheduler->delay(RAMTRON_DELAY_MS);
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}
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// we need to enable writes every time. The WREN bit is
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// automatically reset on completion of the write call
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dev->set_chip_select(true);
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dev->transfer(&RAMTRON_WREN, 1, nullptr, 0);
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dev->set_chip_select(false);
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dev->set_chip_select(true);
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send_offset(RAMTRON_WRITE, offset);
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dev->transfer(buf, size, nullptr, 0);
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dev->set_chip_select(false);
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/*
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verify first 32 bytes of every write using a crc
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*/
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uint8_t rbuf[32] {};
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const uint8_t nverify = MIN(size, sizeof(rbuf));
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uint32_t crc1 = crc_crc32(0, buf, nverify);
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dev->set_chip_select(true);
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send_offset(RAMTRON_READ, offset);
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dev->transfer(nullptr, 0, rbuf, nverify);
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dev->set_chip_select(false);
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uint32_t crc2 = crc_crc32(0, rbuf, nverify);
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if (crc1 == crc2) {
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return true;
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}
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}
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return false;
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}
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