convert RCOutput to new virtual timer interface
cope with SDC vs SDMMC
use new SPIv3 driver. Correct clocks for SDMMCv2.
add STM32L431 support
port ChibiOS config to version 8
support SPIv3 driver model v2 on H7
use currcore in debug options
use new mmc API
disable speed optimizations in the bootloader to save a little flash
upgrade to halconf v8.4
relax constraints on QSP/flash clock.
add support for disabling QSPI reset in main firmware
bootloaders (at least the ones that need to fit into 16kB pages) don't really have the space for this sort of debug.
I figure if you're debugging a bootloader fault you probably have the know-how to get his information yourself based on the code now being excluded, or add it back in.
Also rename from HAL_CRASHDUMP_ENABLE
Removes code based on define rather than creating empty functions. Makes it clearer what's going on in the callers.
hwdef for DevEBoxH7v2
pin definitions for STM32H750
add QSPI to DevEBox bootloader
add external flash to DevEBox
rename EXTERNAL_PROG_FLASH_MB to EXT_FLASH_SIZE_MB
Add support for EXT_FLASH_RESERVE_START_KB and EXT_FLASH_RESERVE_END_KB
Disable HAL_ENABLE_SAVE_PERSISTENT_PARAMS when there is no bootloader flash available
relax storage health status with SD card backend
don't check SD card health unless USE_POSIX
binary sections rearranged on external ram
manage RAMFUNC through ldscript and optimize function placement in external flash
inline timer functions
optimize placement of ChibiOS and functions in ITCM and AXI RAM
fix chibios features on bootloader build with external flash
change H750 memory layout
increase line storage for SD card based parameters
comment external flash linker script
move vtables into DTCM
update ram map for H757
enable crashdump support with external flash
correct bootloader pins and generator on SPRacingH7/DevEBoxH7v2
setup external flash reserve regions
allow different RAM_MAP for external flash on H750 and H757
most ChibiOS boards have a 32 bit timer. This optimisation reduces the
cost of micros() from 0.3us to 0.06us, which is significant in
interrupt handlers and for accurate timing. It takes advantage of the
timer being 32 bit with 1MHz clock
Tom Pittenger
Andrew Tridgell
Andy Piper
Peter Barker
bugobliterator
Mirko Denecke