this changes the heuristics for UART TX DMA allocation to greatly
reduce the chances of DMA contention causing long delays on other
devices
This fixes issues with FETTec driver output and gimbal status messages
as reported by Amilcar and OlliW. The problem is particularly bad when
no GPS is connected to GPS1 on fmuv3 and derived boards (such as
CubeBlack)
key changes:
- remember the contention_counter across begin() calls, as the GPS
calls begin with new baudrates regularly
- added a is_shared() API to Shared_DMA, allowing the UART driver to
avoid TX DMA on shared streams when at low baudrates.
add support for sampling GPIO pins using timer
don't restart pwm group when not doing bi-dir
fix hwdef generation preproc for TIM DMA
decode telemetry at the start of the dshot cycle
calculate dshot pulse separation correctly and ensure we output rapidly enough
calculate dshot min periods and timeouts correctly
refactor dshot_send() into dshot_send_groups()
use bi-dir dshot channel mask
selectively enable bi-dir RC Channels
process bi-dir mask correctly when allocating DMA channels
allow UP and CH DMA channel sharing
optionally enable bidir vars in hwdef.
enable bi-dir dshot in KakuteF7Mini
enable bi-dir dshot in OmnibusF4Pro
enable bi-dir dshot in OmnibusNanoV6
enable bi-dir dshot in MatekF405
enable bi-dir dshot in fmuv5
enable bi-dir dshot in fmuv3
enable bi-dir dshot in OmnibusF7V2
enable bi-dir dshot in OmnibusNanoV6
enable bi-dir dshot in CubeOrange
enable bi-dir dshot in Pixracer
enable bi-dir dshot in mRoPixracerPro
Co-authored-by: bugobliterator <siddharthbharatpurohit@gmail.com>
when both I2C4 and SPI4 are active on a H743 I found that some BDMA
completion interrupts were lost, which resulted in SPI transfer
timeouts. Close inspection of the ChibiOS BDMA, I2Cv3 and SPIv3
drivers did not reveal any issues, but I found that the issue only
happened when the first 4 BDMA streams were used. This change splits
the 4 streams across the first and 2nd half of the BDMA controller,
and that fixes the problem.
This works as there are only 2 peripherals (I2C4 and SPI6) that want
to use BDMA with our current setup. If we ever wish to enable ADC3
(which also uses BDMA) we will need to revisit this issue
Andrew Tridgell
Andy Piper
bugobliterator
Michael du Breuil