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AP_HAL_ChibiOS: properly support CRSF on HEEWING-F405

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update HeeWing F405 README to reflect VTX pinout
This commit is contained in:
Andy Piper 2023-08-04 15:02:11 +02:00 committed by Andrew Tridgell
parent aa5466c6e2
commit 9212a24248
2 changed files with 4 additions and 2 deletions
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3
libraries/AP_HAL_ChibiOS/hwdef/HEEWING-F405/README.md
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@ -26,7 +26,8 @@ receive pin for UARTn. The Tn pin is the transmit pin for UARTn.
- SERIAL0 -> USB - SERIAL0 -> USB
- SERIAL1 -> UART3 (UART1 on casing, DMA-enabled) - SERIAL1 -> UART3 (UART1 on casing, DMA-enabled)
- SERIAL2 -> UART1 (UART2 on casing, DMA-enabled) - SERIAL2 -> UART1 (UART2 on casing, DMA-enabled)
- SERIAL5 -> UART5 (GPS) - SERIAL3 -> UART5 (GPS)
- SERIAL5 -> UART6 (VTX, TX-only)
- SERIAL6 -> UART2 (RCIN RX-only or RX/TX with BRD_ALT_CONFIG=1, DMA-enabled) - SERIAL6 -> UART2 (RCIN RX-only or RX/TX with BRD_ALT_CONFIG=1, DMA-enabled)
## RC Input ## RC Input

3
libraries/AP_HAL_ChibiOS/hwdef/HEEWING-F405/hwdef.dat
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@ -91,6 +91,7 @@ PA3 TIM9_CH2 TIM9 RCININT PULLDOWN
# alternative with PA3 as USART2_RX # alternative with PA3 as USART2_RX
PA3 USART2_RX USART2 ALT(1) PA3 USART2_RX USART2 ALT(1)
DEFAULT_SERIAL6_PROTOCOL SerialProtocol_RCIN
# USART3 - (labelled UART1 on casing) # USART3 - (labelled UART1 on casing)
PC10 USART3_TX USART3 PC10 USART3_TX USART3
@ -104,7 +105,7 @@ PA1 UART4_RX UART4 NODMA
PC12 UART5_TX UART5 PC12 UART5_TX UART5
PD2 UART5_RX UART5 NODMA PD2 UART5_RX UART5 NODMA
# USART6 - (NC) # USART6 - (VTX)
PC6 USART6_TX USART6 NODMA PC6 USART6_TX USART6 NODMA
PC7 USART6_RX USART6 NODMA PC7 USART6_RX USART6 NODMA