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HAL_ChibiOS: reduce DMA count until we can share

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This commit is contained in:
Andrew Tridgell 2019-02-14 17:12:16 +11:00
parent 0c01375799
commit 718cf4377d
1 changed files with 16 additions and 19 deletions
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35
libraries/AP_HAL_ChibiOS/hwdef/Pixhawk4Pro/hwdef.dat
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@ -19,7 +19,7 @@ FLASH_RESERVE_START_KB 128
STM32_VDD 330U STM32_VDD 330U
# order of UARTs (and USB) # order of UARTs (and USB)
UART_ORDER OTG1 UART_ORDER OTG1 USART1 USART2 USART3 UART4 USART6 UART7
define HAL_STORAGE_SIZE 16384 define HAL_STORAGE_SIZE 16384
@ -32,9 +32,6 @@ STM32_VDD 330U
# flash size # flash size
FLASH_SIZE_KB 2048 FLASH_SIZE_KB 2048
# order of UARTs (and USB)
UART_ORDER OTG1 USART1 USART2 USART3 UART4 USART6 UART7
# now we define the pins that USB is connected on # now we define the pins that USB is connected on
PA11 OTG_FS_DM OTG1 PA11 OTG_FS_DM OTG1
PA12 OTG_FS_DP OTG1 PA12 OTG_FS_DP OTG1
@ -87,12 +84,12 @@ PF0 I2C2_SDA I2C2
PH7 I2C3_SCL I2C3 PH7 I2C3_SCL I2C3
PH8 I2C3_SDA I2C3 PH8 I2C3_SDA I2C3
PF14 I2C4_SCL I2C4 # disable I2C4 till we support DMAMUX2
PF15 I2C4_SDA I2C4 #PF14 I2C4_SCL I2C4
#PF15 I2C4_SDA I2C4
# order of I2C buses # order of I2C buses
I2C_ORDER I2C3 I2C1 I2C2 I2C4 I2C_ORDER I2C3 I2C1 I2C2
# enable pins # enable pins
PE3 VDD_3V3_SENSORS_EN OUTPUT HIGH PE3 VDD_3V3_SENSORS_EN OUTPUT HIGH
@ -120,8 +117,8 @@ PD15 DRDY7_EXTERNAL1 INPUT
# UARTs # UARTs
# USART2 is telem1 # USART2 is telem1
PD6 USART2_RX USART2 PD6 USART2_RX USART2 NODMA
PD5 USART2_TX USART2 PD5 USART2_TX USART2 NODMA
PD3 USART2_CTS USART2 PD3 USART2_CTS USART2
PD4 USART2_RTS USART2 PD4 USART2_RTS USART2
@ -130,8 +127,8 @@ PB7 USART1_RX USART1 NODMA
PB6 USART1_TX USART1 NODMA PB6 USART1_TX USART1 NODMA
# USART3 is telem2 # USART3 is telem2
PD9 USART3_RX USART3 PD9 USART3_RX USART3 NODMA
PD8 USART3_TX USART3 PD8 USART3_TX USART3 NODMA
PD11 USART3_CTS USART3 PD11 USART3_CTS USART3
PD12 USART3_RTS USART3 PD12 USART3_RTS USART3
@ -165,12 +162,12 @@ define AP_FEATURE_RTSCTS 1
define AP_FEATURE_SBUS_OUT 1 define AP_FEATURE_SBUS_OUT 1
# PWM AUX channels # PWM AUX channels
PE14 TIM1_CH4 TIM1 PWM(1) GPIO(50) PE14 TIM1_CH4 TIM1 PWM(1) GPIO(50) NODMA
PA10 TIM1_CH3 TIM1 PWM(2) GPIO(51) PA10 TIM1_CH3 TIM1 PWM(2) GPIO(51) NODMA
PE11 TIM1_CH2 TIM1 PWM(3) GPIO(52) PE11 TIM1_CH2 TIM1 PWM(3) GPIO(52) NODMA
PE9 TIM1_CH1 TIM1 PWM(4) GPIO(53) PE9 TIM1_CH1 TIM1 PWM(4) GPIO(53) NODMA
PD13 TIM4_CH2 TIM4 PWM(5) GPIO(54) PD13 TIM4_CH2 TIM4 PWM(5) GPIO(54) NODMA
PD14 TIM4_CH3 TIM4 PWM(6) GPIO(55) PD14 TIM4_CH3 TIM4 PWM(6) GPIO(55) NODMA
# we need to disable DMA on the last 2 FMU channels # we need to disable DMA on the last 2 FMU channels
# as timer 12 doesn't have a TIMn_UP DMA option # as timer 12 doesn't have a TIMn_UP DMA option
PH6 TIM12_CH1 TIM12 PWM(7) GPIO(56) NODMA PH6 TIM12_CH1 TIM12 PWM(7) GPIO(56) NODMA
@ -241,7 +238,7 @@ SPIDEV bmi055_g SPI1 DEVID3 BMI055_G_CS MODE3 10*MHZ 10*MHZ
SPIDEV bmi055_a SPI1 DEVID4 BMI055_A_CS MODE3 10*MHZ 10*MHZ SPIDEV bmi055_a SPI1 DEVID4 BMI055_A_CS MODE3 10*MHZ 10*MHZ
SPIDEV ramtron SPI2 DEVID1 FRAM_CS MODE3 8*MHZ 8*MHZ SPIDEV ramtron SPI2 DEVID1 FRAM_CS MODE3 8*MHZ 8*MHZ
# microSD support # microSD support (disabled for now)
#PC8 SDMMC_D0 SDMMC1 #PC8 SDMMC_D0 SDMMC1
#PC9 SDMMC_D1 SDMMC1 #PC9 SDMMC_D1 SDMMC1
#PC10 SDMMC_D2 SDMMC1 #PC10 SDMMC_D2 SDMMC1