2015-08-11 03:28:43 -03:00
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#include <AP_HAL/AP_HAL.h>
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2020-09-12 16:04:38 -03:00
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#if !defined(HAL_BUILD_AP_PERIPH)
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2015-05-04 03:15:12 -03:00
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#if CONFIG_HAL_BOARD == HAL_BOARD_SITL
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2012-12-17 23:56:21 -04:00
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#include "RCOutput.h"
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2016-01-04 16:19:47 -04:00
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#define ENABLE_DEBUG 0
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#if ENABLE_DEBUG
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2017-01-09 08:31:44 -04:00
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# include <stdio.h>
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# define Debug(fmt, args ...) do {::printf("%s:%d: " fmt "\n", __FUNCTION__, __LINE__, ## args); } while (0)
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2016-01-04 16:19:47 -04:00
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#else
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# define Debug(fmt, args ...)
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#endif
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2012-12-17 23:56:21 -04:00
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2015-05-04 03:15:12 -03:00
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using namespace HALSITL;
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2012-12-17 23:56:21 -04:00
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2016-01-10 02:23:32 -04:00
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void RCOutput::init() {}
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2012-12-17 23:56:21 -04:00
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2016-01-10 02:23:32 -04:00
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void RCOutput::set_freq(uint32_t chmask, uint16_t freq_hz)
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2016-01-04 16:19:47 -04:00
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{
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2017-01-09 08:31:44 -04:00
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Debug("set_freq(0x%04x, %u)\n", static_cast<uint32_t>(chmask), static_cast<uint32_t>(freq_hz));
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2012-12-17 23:56:21 -04:00
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_freq_hz = freq_hz;
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}
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2016-01-10 02:23:32 -04:00
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uint16_t RCOutput::get_freq(uint8_t ch)
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2016-01-04 16:19:47 -04:00
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{
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2012-12-17 23:56:21 -04:00
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return _freq_hz;
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}
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2016-01-10 02:23:32 -04:00
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void RCOutput::enable_ch(uint8_t ch)
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2016-01-04 16:19:47 -04:00
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{
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if (!(_enable_mask & (1U << ch))) {
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Debug("enable_ch(%u)\n", ch);
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}
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2022-03-25 14:52:53 -03:00
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_enable_mask |= (1U << ch);
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2016-01-04 16:19:47 -04:00
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}
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2012-12-17 23:56:21 -04:00
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2016-01-10 02:23:32 -04:00
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void RCOutput::disable_ch(uint8_t ch)
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2016-01-04 16:19:47 -04:00
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{
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2017-01-09 08:31:44 -04:00
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if (_enable_mask & (1U << ch)) {
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2016-01-04 16:19:47 -04:00
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Debug("disable_ch(%u)\n", ch);
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}
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2022-03-25 14:52:53 -03:00
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_enable_mask &= ~(1U << ch);
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2016-01-04 16:19:47 -04:00
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}
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2012-12-17 23:56:21 -04:00
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2016-01-10 02:23:32 -04:00
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void RCOutput::write(uint8_t ch, uint16_t period_us)
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2012-12-17 23:56:21 -04:00
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{
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2017-08-07 09:05:52 -03:00
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_sitlState->output_ready = true;
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2022-03-25 14:52:53 -03:00
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// FIXME: something in sitl is expecting to be able to read and write disabled channels
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if (ch < SITL_NUM_CHANNELS /*&& (_enable_mask & (1U<<ch))*/) {
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2016-10-11 08:02:04 -03:00
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if (_corked) {
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_pending[ch] = period_us;
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} else {
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_sitlState->pwm_output[ch] = period_us;
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}
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2014-11-11 00:15:28 -04:00
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}
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2012-12-17 23:56:21 -04:00
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}
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2016-01-10 02:23:32 -04:00
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uint16_t RCOutput::read(uint8_t ch)
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2014-11-11 00:15:28 -04:00
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{
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2022-03-25 14:52:53 -03:00
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// FIXME: something in sitl is expecting to be able to read and write disabled channels
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if (ch < SITL_NUM_CHANNELS /*&& (_enable_mask & (1U<<ch))*/) {
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2015-05-04 21:59:07 -03:00
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return _sitlState->pwm_output[ch];
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2014-11-11 00:15:28 -04:00
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}
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return 0;
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2012-12-17 23:56:21 -04:00
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}
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2016-01-10 02:23:32 -04:00
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void RCOutput::read(uint16_t* period_us, uint8_t len)
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2012-12-17 23:56:21 -04:00
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{
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2017-01-09 08:31:44 -04:00
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memcpy(period_us, _sitlState->pwm_output, len * sizeof(uint16_t));
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2012-12-17 23:56:21 -04:00
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}
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2012-12-18 05:04:47 -04:00
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2016-10-11 08:02:04 -03:00
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void RCOutput::cork(void)
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{
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2017-04-17 20:40:27 -03:00
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if (!_corked) {
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memcpy(_pending, _sitlState->pwm_output, SITL_NUM_CHANNELS * sizeof(uint16_t));
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_corked = true;
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}
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2016-10-11 08:02:04 -03:00
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}
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void RCOutput::push(void)
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{
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2017-04-17 20:40:27 -03:00
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if (_corked) {
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memcpy(_sitlState->pwm_output, _pending, SITL_NUM_CHANNELS * sizeof(uint16_t));
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_corked = false;
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}
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2021-08-31 20:04:17 -03:00
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SITL::SIM *sitl = AP::sitl();
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2023-01-18 00:19:29 -04:00
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if (sitl && sitl->esc_telem) {
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if (esc_telem == nullptr) {
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esc_telem = new AP_ESC_Telem_SITL;
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}
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if (esc_telem != nullptr) {
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esc_telem->update();
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}
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2021-05-12 21:10:42 -03:00
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}
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2016-10-11 08:02:04 -03:00
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}
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2019-10-30 07:12:17 -03:00
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/*
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Serial LED emulation
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*/
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2021-01-11 22:02:11 -04:00
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bool RCOutput::set_serial_led_num_LEDs(const uint16_t chan, uint8_t num_leds, output_mode mode, uint32_t clock_mask)
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2019-10-30 07:12:17 -03:00
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{
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2020-02-09 06:35:07 -04:00
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if (chan > 15 || num_leds > 64) {
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2019-10-30 07:12:17 -03:00
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return false;
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}
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2021-07-30 07:13:59 -03:00
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SITL::SIM *sitl = AP::sitl();
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2019-10-30 07:12:17 -03:00
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if (sitl) {
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sitl->led.num_leds[chan] = num_leds;
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return true;
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}
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return false;
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}
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2020-02-24 20:54:04 -04:00
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void RCOutput::set_serial_led_rgb_data(const uint16_t chan, int8_t led, uint8_t red, uint8_t green, uint8_t blue)
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2019-10-30 07:12:17 -03:00
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{
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if (chan > 15) {
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return;
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}
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2021-07-30 07:13:59 -03:00
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SITL::SIM *sitl = AP::sitl();
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2020-02-09 06:35:07 -04:00
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if (led == -1) {
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for (uint8_t i=0; i < sitl->led.num_leds[chan]; i++) {
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2020-02-24 20:54:04 -04:00
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set_serial_led_rgb_data(chan, i, red, green, blue);
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2019-10-30 07:12:17 -03:00
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}
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2020-02-09 06:35:07 -04:00
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return;
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}
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if (led < -1 || led >= sitl->led.num_leds[chan]) {
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return;
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}
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if (sitl) {
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sitl->led.rgb[chan][led].rgb[0] = red;
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sitl->led.rgb[chan][led].rgb[1] = green;
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sitl->led.rgb[chan][led].rgb[2] = blue;
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2019-10-30 07:12:17 -03:00
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}
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}
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2020-02-24 20:54:04 -04:00
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void RCOutput::serial_led_send(const uint16_t chan)
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2019-10-30 07:12:17 -03:00
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{
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SITL::SIM *sitl = AP::sitl();
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2019-10-30 07:12:17 -03:00
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if (sitl) {
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sitl->led.send_counter++;
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}
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}
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2020-09-12 16:04:38 -03:00
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#endif //CONFIG_HAL_BOARD == HAL_BOARD_SITL
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2019-11-25 03:02:11 -04:00
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void RCOutput::force_safety_off(void)
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{
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SITL::SIM *sitl = AP::sitl();
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2019-11-25 03:02:11 -04:00
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if (sitl == nullptr) {
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return;
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}
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sitl->force_safety_off();
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}
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bool RCOutput::force_safety_on(void)
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{
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SITL::SIM *sitl = AP::sitl();
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2019-11-25 03:02:11 -04:00
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if (sitl == nullptr) {
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return false;
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}
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return sitl->force_safety_on();
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}
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2020-09-12 16:04:38 -03:00
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#endif //!defined(HAL_BUILD_AP_PERIPH)
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