2012-12-12 18:01:40 -04:00
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#include <AP_HAL.h>
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2012-12-19 02:02:57 -04:00
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#if CONFIG_HAL_BOARD == HAL_BOARD_APM2
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2012-08-27 20:46:07 -03:00
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#include <avr/interrupt.h>
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2012-08-28 01:05:19 -03:00
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#include <AP_HAL.h>
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2012-08-27 20:46:07 -03:00
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#include <AP_HAL_AVR.h>
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#include "RCOutput.h"
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using namespace AP_HAL_AVR;
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2012-08-28 01:05:19 -03:00
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extern const AP_HAL::HAL& hal;
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2012-08-27 20:46:07 -03:00
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/* No init argument required */
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2012-08-28 21:41:49 -03:00
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void APM2RCOutput::init(void* machtnichts) {
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// --------------------- TIMER1: CH_1 and CH_2 -----------------------
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hal.gpio->pinMode(12,GPIO_OUTPUT); // CH_1 (PB6/OC1B)
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hal.gpio->pinMode(11,GPIO_OUTPUT); // CH_2 (PB5/OC1A)
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2012-08-28 01:05:19 -03:00
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// WGM: 1 1 1 0. Clear Timer on Compare, TOP is ICR1.
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// CS11: prescale by 8 => 0.5us tick
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TCCR1A =((1<<WGM11));
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TCCR1B = (1<<WGM13)|(1<<WGM12)|(1<<CS11);
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ICR1 = 40000; // 0.5us tick => 50hz freq
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OCR1A = 0xFFFF; // Init OCR registers to nil output signal
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OCR1B = 0xFFFF;
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2012-08-28 21:41:49 -03:00
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// --------------- TIMER4: CH_3, CH_4, and CH_5 ---------------------
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hal.gpio->pinMode(8,GPIO_OUTPUT); // CH_3 (PH5/OC4C)
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hal.gpio->pinMode(7,GPIO_OUTPUT); // CH_4 (PH4/OC4B)
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hal.gpio->pinMode(6,GPIO_OUTPUT); // CH_5 (PH3/OC4A)
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2012-08-28 01:05:19 -03:00
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// WGM: 1 1 1 0. Clear Timer on Compare, TOP is ICR4.
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// CS41: prescale by 8 => 0.5us tick
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TCCR4A =((1<<WGM41));
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TCCR4B = (1<<WGM43)|(1<<WGM42)|(1<<CS41);
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OCR4A = 0xFFFF; // Init OCR registers to nil output signal
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OCR4B = 0xFFFF;
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OCR4C = 0xFFFF;
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ICR4 = 40000; // 0.5us tick => 50hz freq
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2012-08-28 21:41:49 -03:00
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//--------------- TIMER3: CH_6, CH_7, and CH_8 ----------------------
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hal.gpio->pinMode(3,GPIO_OUTPUT); // CH_6 (PE5/OC3C)
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hal.gpio->pinMode(2,GPIO_OUTPUT); // CH_7 (PE4/OC3B)
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hal.gpio->pinMode(5,GPIO_OUTPUT); // CH_8 (PE3/OC3A)
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2012-08-28 01:05:19 -03:00
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// WGM: 1 1 1 0. Clear timer on Compare, TOP is ICR3
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// CS31: prescale by 8 => 0.5us tick
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TCCR3A =((1<<WGM31));
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TCCR3B = (1<<WGM33)|(1<<WGM32)|(1<<CS31);
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OCR3A = 0xFFFF; // Init OCR registers to nil output signal
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OCR3B = 0xFFFF;
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OCR3C = 0xFFFF;
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ICR3 = 40000; // 0.5us tick => 50hz freq
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2012-08-28 21:41:49 -03:00
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//--------------- TIMER5: CH_10, and CH_11 ---------------
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// NB TIMER5 is shared with PPM input from RCInput_APM2.cpp
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2012-08-28 01:05:19 -03:00
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// The TIMER5 registers are assumed to be setup already.
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2012-08-28 21:41:49 -03:00
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hal.gpio->pinMode(45, GPIO_OUTPUT); // CH_10 (PL4/OC5B)
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hal.gpio->pinMode(44, GPIO_OUTPUT); // CH_11 (PL5/OC5C)
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2012-08-27 20:46:07 -03:00
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}
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/* Output freq (1/period) control */
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void APM2RCOutput::set_freq(uint32_t chmask, uint16_t freq_hz) {
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2012-08-28 01:05:19 -03:00
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uint16_t icr = _timer_period(freq_hz);
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if ((chmask & ( _BV(CH_1) | _BV(CH_2))) != 0) {
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ICR1 = icr;
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}
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2012-08-27 20:46:07 -03:00
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2012-08-28 01:05:19 -03:00
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if ((chmask & ( _BV(CH_3) | _BV(CH_4) | _BV(CH_5))) != 0) {
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ICR4 = icr;
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}
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if ((chmask & ( _BV(CH_6) | _BV(CH_7) | _BV(CH_8))) != 0) {
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ICR3 = icr;
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}
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2012-08-27 20:46:07 -03:00
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}
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uint16_t APM2RCOutput::get_freq(uint8_t ch) {
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uint16_t icr;
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switch (ch) {
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case CH_1:
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case CH_2:
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icr = ICR1;
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break;
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case CH_3:
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case CH_4:
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case CH_5:
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icr = ICR4;
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break;
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case CH_6:
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case CH_7:
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case CH_8:
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icr = ICR3;
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break;
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2012-08-28 22:08:23 -03:00
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/* CH_10 and CH_11 share TIMER5 with input capture.
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* The period is specified in OCR5A rater than the ICR. */
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2012-08-28 21:41:49 -03:00
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case CH_10:
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case CH_11:
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icr = OCR5A;
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break;
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2012-08-28 01:05:19 -03:00
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default:
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return 0;
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}
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2012-08-28 21:41:49 -03:00
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/* transform to period by inverse of _time_period(icr). */
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return (2000000UL / icr);
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2012-08-27 20:46:07 -03:00
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}
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/* Output active/highZ control, either by single channel at a time
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* or a mask of channels */
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void APM2RCOutput::enable_ch(uint8_t ch) {
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switch(ch) {
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case 0: TCCR1A |= (1<<COM1B1); break; // CH_1 : OC1B
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case 1: TCCR1A |= (1<<COM1A1); break; // CH_2 : OC1A
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case 2: TCCR4A |= (1<<COM4C1); break; // CH_3 : OC4C
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case 3: TCCR4A |= (1<<COM4B1); break; // CH_4 : OC4B
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case 4: TCCR4A |= (1<<COM4A1); break; // CH_5 : OC4A
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case 5: TCCR3A |= (1<<COM3C1); break; // CH_6 : OC3C
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case 6: TCCR3A |= (1<<COM3B1); break; // CH_7 : OC3B
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case 7: TCCR3A |= (1<<COM3A1); break; // CH_8 : OC3A
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case 9: TCCR5A |= (1<<COM5B1); break; // CH_10 : OC5B
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case 10: TCCR5A |= (1<<COM5C1); break; // CH_11 : OC5C
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}
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2012-08-27 20:46:07 -03:00
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}
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void APM2RCOutput::enable_mask(uint32_t chmask) {
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2012-08-28 01:05:19 -03:00
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for (int i = 0; i < 32; i++) {
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uint32_t c = chmask >> i;
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if (c & 1) {
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enable_ch(i);
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}
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}
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2012-08-27 20:46:07 -03:00
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}
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void APM2RCOutput::disable_ch(uint8_t ch) {
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2012-08-28 01:05:19 -03:00
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switch(ch) {
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case 0: TCCR1A &= ~(1<<COM1B1); break; // CH_1 : OC1B
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case 1: TCCR1A &= ~(1<<COM1A1); break; // CH_2 : OC1A
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case 2: TCCR4A &= ~(1<<COM4C1); break; // CH_3 : OC4C
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case 3: TCCR4A &= ~(1<<COM4B1); break; // CH_4 : OC4B
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case 4: TCCR4A &= ~(1<<COM4A1); break; // CH_5 : OC4A
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case 5: TCCR3A &= ~(1<<COM3C1); break; // CH_6 : OC3C
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case 6: TCCR3A &= ~(1<<COM3B1); break; // CH_7 : OC3B
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case 7: TCCR3A &= ~(1<<COM3A1); break; // CH_8 : OC3A
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case 9: TCCR5A &= ~(1<<COM5B1); break; // CH_10 : OC5B
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case 10: TCCR5A &= ~(1<<COM5C1); break; // CH_11 : OC5C
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}
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2012-08-27 20:46:07 -03:00
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}
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void APM2RCOutput::disable_mask(uint32_t chmask) {
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for (int i = 0; i < 32; i++) {
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if ((chmask >> i) & 1) {
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disable_ch(i);
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}
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}
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}
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2012-08-27 20:46:07 -03:00
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2012-08-28 01:05:19 -03:00
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/* constrain pwm to be between min and max pulsewidth. */
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static inline uint16_t constrain_period(uint16_t p) {
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if (p > RC_INPUT_MAX_PULSEWIDTH) return RC_INPUT_MAX_PULSEWIDTH;
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if (p < RC_INPUT_MIN_PULSEWIDTH) return RC_INPUT_MIN_PULSEWIDTH;
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return p;
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2012-08-27 20:46:07 -03:00
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}
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/* Output, either single channel or bulk array of channels */
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void APM2RCOutput::write(uint8_t ch, uint16_t period_us) {
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/* constrain, then scale from 1us resolution (input units)
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* to 0.5us (timer units) */
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uint16_t pwm = constrain_period(period_us) << 1;
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switch(ch)
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{
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case 0: OCR1B=pwm; break; // out1
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case 1: OCR1A=pwm; break; // out2
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case 2: OCR4C=pwm; break; // out3
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case 3: OCR4B=pwm; break; // out4
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case 4: OCR4A=pwm; break; // out5
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case 5: OCR3C=pwm; break; // out6
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case 6: OCR3B=pwm; break; // out7
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case 7: OCR3A=pwm; break; // out8
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case 9: OCR5B=pwm; break; // out10
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case 10: OCR5C=pwm; break; // out11
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}
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2012-08-27 20:46:07 -03:00
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}
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2012-08-28 01:05:19 -03:00
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void APM2RCOutput::write(uint8_t ch, uint16_t* period_us, uint8_t len) {
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for (int i = 0; i < len; i++) {
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write(i + ch, period_us[i]);
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}
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2012-08-27 20:46:07 -03:00
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}
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/* Read back current output state, as either single channel or
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* array of channels. */
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uint16_t APM2RCOutput::read(uint8_t ch) {
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2012-08-28 01:05:19 -03:00
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uint16_t pwm=0;
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switch(ch) {
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case 0: pwm=OCR1B; break; // out1
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case 1: pwm=OCR1A; break; // out2
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case 2: pwm=OCR4C; break; // out3
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case 3: pwm=OCR4B; break; // out4
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case 4: pwm=OCR4A; break; // out5
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case 5: pwm=OCR3C; break; // out6
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case 6: pwm=OCR3B; break; // out7
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case 7: pwm=OCR3A; break; // out8
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case 9: pwm=OCR5B; break; // out10
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case 10: pwm=OCR5C; break; // out11
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}
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/* scale from 0.5us resolution (timer units) to 1us units */
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return pwm>>1;
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2012-08-27 20:46:07 -03:00
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}
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2012-08-28 01:05:19 -03:00
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void APM2RCOutput::read(uint16_t* period_us, uint8_t len) {
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for (int i = 0; i < len; i++) {
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period_us[i] = read(i);
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}
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2012-08-27 20:46:07 -03:00
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}
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2012-08-28 01:05:19 -03:00
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uint16_t APM2RCOutput::_timer_period(uint16_t speed_hz) {
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return 2000000UL / speed_hz;
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}
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2012-12-12 18:01:40 -04:00
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#endif
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