2014-03-31 14:29:33 -03:00
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/// -*- tab-width: 4; Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil -*-
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2015-08-11 03:28:43 -03:00
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#include <AP_HAL/AP_HAL.h>
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2014-03-31 14:29:33 -03:00
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#if CONFIG_HAL_BOARD == HAL_BOARD_VRBRAIN
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#include "RCOutput.h"
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <drivers/drv_pwm_output.h>
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extern const AP_HAL::HAL& hal;
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using namespace VRBRAIN;
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void VRBRAINRCOutput::init(void* unused)
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{
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_perf_rcout = perf_alloc(PC_ELAPSED, "APM_rcout");
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_pwm_fd = open(PWM_OUTPUT_DEVICE_PATH, O_RDWR);
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if (_pwm_fd == -1) {
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hal.scheduler->panic("Unable to open " PWM_OUTPUT_DEVICE_PATH);
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}
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if (ioctl(_pwm_fd, PWM_SERVO_ARM, 0) != 0) {
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hal.console->printf("RCOutput: Unable to setup IO arming\n");
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}
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if (ioctl(_pwm_fd, PWM_SERVO_SET_ARM_OK, 0) != 0) {
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hal.console->printf("RCOutput: Unable to setup IO arming OK\n");
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}
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_rate_mask = 0;
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2014-06-27 11:32:03 -03:00
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2014-03-31 14:29:33 -03:00
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_servo_count = 0;
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2014-06-27 11:32:03 -03:00
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2014-03-31 14:29:33 -03:00
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if (ioctl(_pwm_fd, PWM_SERVO_GET_COUNT, (unsigned long)&_servo_count) != 0) {
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hal.console->printf("RCOutput: Unable to get servo count\n");
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return;
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}
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}
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void VRBRAINRCOutput::_init_alt_channels(void)
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{
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2014-06-27 11:32:03 -03:00
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2014-03-31 14:29:33 -03:00
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}
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void VRBRAINRCOutput::set_freq(uint32_t chmask, uint16_t freq_hz)
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{
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// we can't set this per channel yet
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if (freq_hz > 50) {
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// we're being asked to set the alt rate
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if (ioctl(_pwm_fd, PWM_SERVO_SET_UPDATE_RATE, (unsigned long)freq_hz) != 0) {
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hal.console->printf("RCOutput: Unable to set alt rate to %uHz\n", (unsigned)freq_hz);
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return;
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}
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_freq_hz = freq_hz;
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}
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/* work out the new rate mask. The PX4IO board has 3 groups of servos.
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Group 0: channels 0 1
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Group 1: channels 4 5 6 7
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Group 2: channels 2 3
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Channels within a group must be set to the same rate.
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For the moment we never set the channels above 8 to more than
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50Hz
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*/
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if (freq_hz > 50) {
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// we are setting high rates on the given channels
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_rate_mask |= chmask & 0xFF;
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if (_rate_mask & 0x07) {
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_rate_mask |= 0x07;
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}
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if (_rate_mask & 0x38) {
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_rate_mask |= 0x38;
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}
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if (_rate_mask & 0xC0) {
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_rate_mask |= 0xC0;
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}
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} else {
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// we are setting low rates on the given channels
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if (chmask & 0x07) {
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_rate_mask &= ~0x07;
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}
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if (chmask & 0x38) {
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_rate_mask &= ~0x38;
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}
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if (chmask & 0xC0) {
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_rate_mask &= ~0xC0;
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}
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}
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if (ioctl(_pwm_fd, PWM_SERVO_SET_SELECT_UPDATE_RATE, _rate_mask) != 0) {
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hal.console->printf("RCOutput: Unable to set alt rate mask to 0x%x\n", (unsigned)_rate_mask);
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}
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}
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uint16_t VRBRAINRCOutput::get_freq(uint8_t ch)
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{
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if (_rate_mask & (1U<<ch)) {
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return _freq_hz;
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}
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return 50;
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}
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void VRBRAINRCOutput::enable_ch(uint8_t ch)
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{
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_enabled_channels |= (1U<<ch);
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}
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void VRBRAINRCOutput::disable_ch(uint8_t ch)
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{
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_enabled_channels &= ~(1U<<ch);
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}
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void VRBRAINRCOutput::set_safety_pwm(uint32_t chmask, uint16_t period_us)
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{
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struct pwm_output_values pwm_values;
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memset(&pwm_values, 0, sizeof(pwm_values));
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for (uint8_t i=0; i<_servo_count; i++) {
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if ((1UL<<i) & chmask) {
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pwm_values.values[i] = period_us;
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}
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pwm_values.channel_count++;
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}
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int ret = ioctl(_pwm_fd, PWM_SERVO_SET_DISARMED_PWM, (long unsigned int)&pwm_values);
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if (ret != OK) {
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hal.console->printf("Failed to setup disarmed PWM for 0x%08x to %u\n", (unsigned)chmask, period_us);
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}
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}
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2014-05-30 17:58:34 -03:00
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void VRBRAINRCOutput::set_failsafe_pwm(uint32_t chmask, uint16_t period_us)
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{
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struct pwm_output_values pwm_values;
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memset(&pwm_values, 0, sizeof(pwm_values));
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for (uint8_t i=0; i<_servo_count; i++) {
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if ((1UL<<i) & chmask) {
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pwm_values.values[i] = period_us;
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}
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pwm_values.channel_count++;
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}
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int ret = ioctl(_pwm_fd, PWM_SERVO_SET_FAILSAFE_PWM, (long unsigned int)&pwm_values);
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if (ret != OK) {
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hal.console->printf("Failed to setup failsafe PWM for 0x%08x to %u\n", (unsigned)chmask, period_us);
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}
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}
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2014-09-14 05:24:13 -03:00
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bool VRBRAINRCOutput::force_safety_on(void)
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{
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int ret = ioctl(_pwm_fd, PWM_SERVO_SET_FORCE_SAFETY_ON, 0);
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return (ret == OK);
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}
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2014-03-31 14:29:33 -03:00
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void VRBRAINRCOutput::force_safety_off(void)
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{
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int ret = ioctl(_pwm_fd, PWM_SERVO_SET_FORCE_SAFETY_OFF, 0);
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if (ret != OK) {
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hal.console->printf("Failed to force safety off\n");
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}
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}
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void VRBRAINRCOutput::write(uint8_t ch, uint16_t period_us)
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{
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2014-06-27 11:32:03 -03:00
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if (ch >= _servo_count) {
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2014-03-31 14:29:33 -03:00
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return;
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}
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if (!(_enabled_channels & (1U<<ch))) {
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// not enabled
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return;
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}
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if (ch >= _max_channel) {
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_max_channel = ch + 1;
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}
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if (period_us != _period[ch]) {
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_period[ch] = period_us;
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_need_update = true;
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2014-06-27 11:32:03 -03:00
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up_pwm_servo_set(ch, period_us);
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2014-03-31 14:29:33 -03:00
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}
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}
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void VRBRAINRCOutput::write(uint8_t ch, uint16_t* period_us, uint8_t len)
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{
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for (uint8_t i=0; i<len; i++) {
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write(i, period_us[i]);
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}
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}
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uint16_t VRBRAINRCOutput::read(uint8_t ch)
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{
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if (ch >= VRBRAIN_NUM_OUTPUT_CHANNELS) {
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return 0;
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}
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return _period[ch];
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}
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void VRBRAINRCOutput::read(uint16_t* period_us, uint8_t len)
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{
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for (uint8_t i=0; i<len; i++) {
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period_us[i] = read(i);
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}
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}
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void VRBRAINRCOutput::_timer_tick(void)
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{
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uint32_t now = hal.scheduler->micros();
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// always send at least at 20Hz, otherwise the IO board may think
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// we are dead
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if (now - _last_output > 50000) {
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_need_update = true;
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}
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if (_need_update && _pwm_fd != -1) {
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_need_update = false;
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perf_begin(_perf_rcout);
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2014-07-02 05:12:57 -03:00
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::write(_pwm_fd, _period, _max_channel*sizeof(_period[0]));
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2014-03-31 14:29:33 -03:00
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perf_end(_perf_rcout);
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_last_output = now;
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}
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}
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#endif // CONFIG_HAL_BOARD
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