2018-01-05 02:19:51 -04:00
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/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "I2CDevice.h"
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#include <AP_HAL/AP_HAL.h>
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#include <AP_Math/AP_Math.h>
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#include "Util.h"
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2020-10-27 22:01:14 -03:00
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#include "GPIO.h"
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2018-08-07 05:47:10 -03:00
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2019-05-26 22:45:30 -03:00
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#if HAL_USE_I2C == TRUE && defined(HAL_I2C_DEVICE_LIST)
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2018-08-07 05:47:10 -03:00
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2018-01-05 02:19:51 -04:00
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#include "Scheduler.h"
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2018-05-30 01:22:49 -03:00
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#include "hwdef/common/stm32_util.h"
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2019-08-23 21:03:52 -03:00
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#include <AP_InternalError/AP_InternalError.h>
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2018-01-05 02:19:51 -04:00
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#include "ch.h"
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#include "hal.h"
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2018-01-11 19:20:49 -04:00
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static const struct I2CInfo {
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struct I2CDriver *i2c;
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2020-10-27 22:01:14 -03:00
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uint8_t instance;
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2018-01-11 19:20:49 -04:00
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uint8_t dma_channel_rx;
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uint8_t dma_channel_tx;
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2018-11-15 06:25:29 -04:00
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ioline_t scl_line;
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ioline_t sda_line;
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2018-01-11 19:20:49 -04:00
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} I2CD[] = { HAL_I2C_DEVICE_LIST };
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2018-01-05 02:19:51 -04:00
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using namespace ChibiOS;
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2018-01-09 17:18:28 -04:00
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extern const AP_HAL::HAL& hal;
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2018-01-05 02:19:51 -04:00
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2018-08-02 20:27:17 -03:00
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I2CBus I2CDeviceManager::businfo[ARRAY_SIZE(I2CD)];
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2018-01-05 02:19:51 -04:00
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2018-01-19 18:01:06 -04:00
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#ifndef HAL_I2C_BUS_BASE
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#define HAL_I2C_BUS_BASE 0
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#endif
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2018-01-19 18:04:35 -04:00
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// default to 100kHz clock for maximum reliability. This can be
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// changed in hwdef.dat
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#ifndef HAL_I2C_MAX_CLOCK
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#define HAL_I2C_MAX_CLOCK 100000
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#endif
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2018-04-26 15:56:40 -03:00
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// values calculated with STM32CubeMX tool, PCLK=54MHz
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2021-05-06 21:56:53 -03:00
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#ifndef HAL_I2C_F7_100_TIMINGR
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#define HAL_I2C_F7_100_TIMINGR 0x30812E3E
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#endif
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#ifndef HAL_I2C_F7_400_TIMINGR
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2018-04-26 15:56:40 -03:00
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#define HAL_I2C_F7_400_TIMINGR 0x6000030D
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2021-05-06 21:56:53 -03:00
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#endif
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2018-04-26 15:56:40 -03:00
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2021-05-06 21:56:53 -03:00
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#ifndef HAL_I2C_H7_100_TIMINGR
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2019-12-29 23:06:05 -04:00
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#define HAL_I2C_H7_100_TIMINGR 0x00707CBB
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2021-05-06 21:56:53 -03:00
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#endif
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#ifndef HAL_I2C_H7_400_TIMINGR
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2019-12-29 23:06:05 -04:00
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#define HAL_I2C_H7_400_TIMINGR 0x00300F38
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2021-05-06 21:56:53 -03:00
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#endif
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2019-12-29 23:06:05 -04:00
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2018-11-15 06:25:29 -04:00
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/*
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enable clear (toggling SCL) on I2C bus timeouts which leave SDA stuck low
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*/
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#ifndef HAL_I2C_CLEAR_ON_TIMEOUT
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#define HAL_I2C_CLEAR_ON_TIMEOUT 1
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#endif
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2018-01-10 00:26:05 -04:00
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// get a handle for DMA sharing DMA channels with other subsystems
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void I2CBus::dma_init(void)
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{
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2018-06-04 08:27:54 -03:00
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chMtxObjectInit(&dma_lock);
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2019-10-20 10:31:12 -03:00
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dma_handle = new Shared_DMA(I2CD[busnum].dma_channel_tx, I2CD[busnum].dma_channel_rx,
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2018-03-14 03:06:30 -03:00
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FUNCTOR_BIND_MEMBER(&I2CBus::dma_allocate, void, Shared_DMA *),
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2019-10-20 10:31:12 -03:00
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FUNCTOR_BIND_MEMBER(&I2CBus::dma_deallocate, void, Shared_DMA *));
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2018-01-10 00:26:05 -04:00
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}
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2018-02-05 15:40:05 -04:00
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// Clear Bus to avoid bus lockup
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void I2CBus::clear_all()
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{
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2018-11-15 06:25:29 -04:00
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for (uint8_t i=0; i<ARRAY_SIZE(I2CD); i++) {
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clear_bus(i);
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}
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2018-02-05 15:40:05 -04:00
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}
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2018-11-15 06:25:29 -04:00
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/*
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clear a stuck bus (bus held by a device that is holding SDA low) by
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clocking out pulses on SCL to let the device complete its
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transaction
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*/
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void I2CBus::clear_bus(uint8_t busidx)
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2018-02-05 15:40:05 -04:00
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{
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2019-05-26 22:45:30 -03:00
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#if HAL_I2C_CLEAR_ON_TIMEOUT
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2018-11-15 06:25:29 -04:00
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const struct I2CInfo &info = I2CD[busidx];
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2020-10-27 22:01:14 -03:00
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const ioline_t scl_line = GPIO::resolve_alt_config(info.scl_line, PERIPH_TYPE::I2C_SCL, info.instance);
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if (scl_line == 0) {
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return;
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}
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const iomode_t mode_saved = palReadLineMode(scl_line);
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palSetLineMode(scl_line, PAL_MODE_OUTPUT_PUSHPULL);
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2018-11-15 06:25:29 -04:00
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for(uint8_t j = 0; j < 20; j++) {
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2020-10-27 22:01:14 -03:00
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palToggleLine(scl_line);
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2018-11-15 06:25:29 -04:00
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hal.scheduler->delay_microseconds(10);
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2018-02-05 15:40:05 -04:00
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}
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2020-10-27 22:01:14 -03:00
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palSetLineMode(scl_line, mode_saved);
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2019-05-26 22:45:30 -03:00
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#endif
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2018-11-15 06:25:29 -04:00
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}
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2019-05-26 22:45:30 -03:00
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#if HAL_I2C_CLEAR_ON_TIMEOUT
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2018-11-15 06:25:29 -04:00
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/*
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read SDA on a bus, to check if it may be stuck
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*/
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uint8_t I2CBus::read_sda(uint8_t busidx)
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{
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const struct I2CInfo &info = I2CD[busidx];
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2020-10-27 22:01:14 -03:00
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const ioline_t sda_line = GPIO::resolve_alt_config(info.sda_line, PERIPH_TYPE::I2C_SDA, info.instance);
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if (sda_line == 0) {
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return 0;
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}
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const iomode_t mode_saved = palReadLineMode(sda_line);
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palSetLineMode(sda_line, PAL_MODE_INPUT);
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uint8_t ret = palReadLine(sda_line);
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palSetLineMode(sda_line, mode_saved);
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2018-11-15 06:25:29 -04:00
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return ret;
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2018-02-05 15:40:05 -04:00
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}
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2019-05-26 22:45:30 -03:00
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#endif
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2018-02-05 15:40:05 -04:00
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2018-01-10 00:26:05 -04:00
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// setup I2C buses
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I2CDeviceManager::I2CDeviceManager(void)
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{
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2018-08-02 20:27:17 -03:00
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for (uint8_t i=0; i<ARRAY_SIZE(I2CD); i++) {
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2018-01-10 00:26:05 -04:00
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businfo[i].busnum = i;
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businfo[i].dma_init();
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/*
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setup default I2C config. As each device is opened we will
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drop the speed to be the minimum speed requested
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*/
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2018-04-26 15:56:40 -03:00
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businfo[i].busclock = HAL_I2C_MAX_CLOCK;
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2021-07-20 23:43:56 -03:00
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#if defined(STM32F7) || defined(STM32F3) || defined(STM32G4)
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2018-04-26 15:56:40 -03:00
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if (businfo[i].busclock <= 100000) {
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businfo[i].i2ccfg.timingr = HAL_I2C_F7_100_TIMINGR;
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businfo[i].busclock = 100000;
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} else {
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businfo[i].i2ccfg.timingr = HAL_I2C_F7_400_TIMINGR;
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businfo[i].busclock = 400000;
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}
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2019-12-29 23:06:05 -04:00
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#elif defined(STM32H7)
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if (businfo[i].busclock <= 100000) {
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businfo[i].i2ccfg.timingr = HAL_I2C_H7_100_TIMINGR;
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businfo[i].busclock = 100000;
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} else {
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businfo[i].i2ccfg.timingr = HAL_I2C_H7_400_TIMINGR;
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businfo[i].busclock = 400000;
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}
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#else // F1 or F4
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2018-01-10 00:26:05 -04:00
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businfo[i].i2ccfg.op_mode = OPMODE_I2C;
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2018-04-26 15:56:40 -03:00
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businfo[i].i2ccfg.clock_speed = businfo[i].busclock;
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2018-01-19 18:04:35 -04:00
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if (businfo[i].i2ccfg.clock_speed <= 100000) {
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businfo[i].i2ccfg.duty_cycle = STD_DUTY_CYCLE;
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} else {
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businfo[i].i2ccfg.duty_cycle = FAST_DUTY_CYCLE_2;
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}
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2018-04-26 15:56:40 -03:00
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#endif
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2018-01-10 00:26:05 -04:00
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}
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}
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I2CDevice::I2CDevice(uint8_t busnum, uint8_t address, uint32_t bus_clock, bool use_smbus, uint32_t timeout_ms) :
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2018-01-05 02:19:51 -04:00
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_retries(2),
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2018-01-10 00:26:05 -04:00
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_address(address),
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_use_smbus(use_smbus),
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_timeout_ms(timeout_ms),
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bus(I2CDeviceManager::businfo[busnum])
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2018-01-05 02:19:51 -04:00
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{
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2018-01-19 18:01:06 -04:00
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set_device_bus(busnum+HAL_I2C_BUS_BASE);
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2018-01-05 02:19:51 -04:00
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set_device_address(address);
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asprintf(&pname, "I2C:%u:%02x",
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2018-01-10 00:26:05 -04:00
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(unsigned)busnum, (unsigned)address);
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2018-04-26 15:56:40 -03:00
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if (bus_clock < bus.busclock) {
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2021-07-20 23:43:56 -03:00
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32F3) || defined(STM32G4)
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2018-04-26 15:56:40 -03:00
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if (bus_clock <= 100000) {
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bus.i2ccfg.timingr = HAL_I2C_F7_100_TIMINGR;
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bus.busclock = 100000;
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}
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#else
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2018-01-10 00:26:05 -04:00
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bus.i2ccfg.clock_speed = bus_clock;
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2018-04-26 15:56:40 -03:00
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bus.busclock = bus_clock;
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2018-01-10 00:26:05 -04:00
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if (bus_clock <= 100000) {
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bus.i2ccfg.duty_cycle = STD_DUTY_CYCLE;
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}
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2018-04-26 15:56:40 -03:00
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#endif
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hal.console->printf("I2C%u clock %ukHz\n", busnum, unsigned(bus.busclock/1000));
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2018-01-05 02:19:51 -04:00
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}
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}
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I2CDevice::~I2CDevice()
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{
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2018-05-30 02:18:29 -03:00
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#if 0
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2019-10-20 10:31:12 -03:00
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printf("I2C device bus %u address 0x%02x closed\n",
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2018-01-10 00:26:05 -04:00
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(unsigned)bus.busnum, (unsigned)_address);
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2018-05-30 02:18:29 -03:00
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#endif
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2018-01-05 02:19:51 -04:00
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free(pname);
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}
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/*
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2018-08-01 22:48:12 -03:00
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allocate DMA channel, nothing to do, as we don't keep the bus active between transactions
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2018-01-05 02:19:51 -04:00
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*/
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2018-03-14 03:06:30 -03:00
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void I2CBus::dma_allocate(Shared_DMA *ctx)
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2018-01-05 02:19:51 -04:00
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{
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}
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/*
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deallocate DMA channel
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*/
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2018-03-14 03:06:30 -03:00
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void I2CBus::dma_deallocate(Shared_DMA *)
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2018-01-05 02:19:51 -04:00
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{
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}
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bool I2CDevice::transfer(const uint8_t *send, uint32_t send_len,
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uint8_t *recv, uint32_t recv_len)
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{
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2018-02-06 02:48:10 -04:00
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if (!bus.semaphore.check_owner()) {
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2019-05-26 22:45:30 -03:00
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hal.console->printf("I2C: not owner of 0x%x for addr 0x%02x\n", (unsigned)get_bus_id(), _address);
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2018-02-06 02:48:10 -04:00
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return false;
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}
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2019-10-20 10:31:12 -03:00
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2021-07-20 23:43:56 -03:00
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#if defined(STM32F7) || defined(STM32H7) || defined(STM32F3) || defined(STM32G4)
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2018-04-26 15:56:40 -03:00
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if (_use_smbus) {
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bus.i2ccfg.cr1 |= I2C_CR1_SMBHEN;
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} else {
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bus.i2ccfg.cr1 &= ~I2C_CR1_SMBHEN;
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}
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#else
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2018-01-10 00:26:05 -04:00
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if (_use_smbus) {
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bus.i2ccfg.op_mode = OPMODE_SMBUS_HOST;
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} else {
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bus.i2ccfg.op_mode = OPMODE_I2C;
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2018-01-05 02:19:51 -04:00
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}
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2018-04-26 15:56:40 -03:00
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#endif
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2018-05-30 01:22:49 -03:00
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2018-01-05 02:19:51 -04:00
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if (_split_transfers) {
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/*
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splitting the transfer() into two pieces avoids a stop condition
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with SCL low which is not supported on some devices (such as
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LidarLite blue label)
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*/
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if (send && send_len) {
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if (!_transfer(send, send_len, nullptr, 0)) {
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return false;
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}
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}
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if (recv && recv_len) {
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if (!_transfer(nullptr, 0, recv, recv_len)) {
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return false;
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}
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}
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} else {
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// combined transfer
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if (!_transfer(send, send_len, recv, recv_len)) {
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return false;
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}
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}
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return true;
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}
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bool I2CDevice::_transfer(const uint8_t *send, uint32_t send_len,
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uint8_t *recv, uint32_t recv_len)
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{
|
2018-02-06 02:48:10 -04:00
|
|
|
i2cAcquireBus(I2CD[bus.busnum].i2c);
|
2018-06-02 00:27:02 -03:00
|
|
|
|
2020-01-17 00:22:44 -04:00
|
|
|
if (!bus.bouncebuffer_setup(send, send_len, recv, recv_len)) {
|
|
|
|
i2cReleaseBus(I2CD[bus.busnum].i2c);
|
|
|
|
return false;
|
|
|
|
}
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
for(uint8_t i=0 ; i <= _retries; i++) {
|
2018-01-09 17:18:28 -04:00
|
|
|
int ret;
|
2018-01-05 02:19:51 -04:00
|
|
|
// calculate a timeout as twice the expected transfer time, and set as min of 4ms
|
2019-08-25 08:49:53 -03:00
|
|
|
uint32_t timeout_ms = 1+2*(((8*1000000UL/bus.busclock)*(send_len+recv_len))/1000);
|
2018-01-10 00:26:05 -04:00
|
|
|
timeout_ms = MAX(timeout_ms, _timeout_ms);
|
2018-06-08 02:43:07 -03:00
|
|
|
|
2018-08-01 22:48:12 -03:00
|
|
|
// we get the lock and start the bus inside the retry loop to
|
|
|
|
// allow us to give up the DMA channel to an SPI device on
|
|
|
|
// retries
|
2018-07-12 01:12:02 -03:00
|
|
|
bus.dma_handle->lock();
|
|
|
|
|
2018-08-01 22:48:12 -03:00
|
|
|
i2cStart(I2CD[bus.busnum].i2c, &bus.i2ccfg);
|
2018-02-06 02:48:10 -04:00
|
|
|
osalDbgAssert(I2CD[bus.busnum].i2c->state == I2C_READY, "i2cStart state");
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2019-05-16 04:57:35 -03:00
|
|
|
osalSysLock();
|
|
|
|
hal.util->persistent_data.i2c_count++;
|
|
|
|
osalSysUnlock();
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
if(send_len == 0) {
|
2018-06-02 12:56:42 -03:00
|
|
|
ret = i2cMasterReceiveTimeout(I2CD[bus.busnum].i2c, _address, recv, recv_len, chTimeMS2I(timeout_ms));
|
2018-01-05 02:19:51 -04:00
|
|
|
} else {
|
2018-06-02 00:27:02 -03:00
|
|
|
ret = i2cMasterTransmitTimeout(I2CD[bus.busnum].i2c, _address, send, send_len,
|
2018-06-02 12:56:42 -03:00
|
|
|
recv, recv_len, chTimeMS2I(timeout_ms));
|
2018-05-31 22:37:14 -03:00
|
|
|
}
|
2018-07-12 01:12:02 -03:00
|
|
|
|
2019-05-24 05:26:03 -03:00
|
|
|
i2cSoftStop(I2CD[bus.busnum].i2c);
|
2018-08-01 22:48:12 -03:00
|
|
|
osalDbgAssert(I2CD[bus.busnum].i2c->state == I2C_STOP, "i2cStart state");
|
2019-08-23 21:03:52 -03:00
|
|
|
|
2018-07-12 01:12:02 -03:00
|
|
|
bus.dma_handle->unlock();
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2019-08-23 21:03:52 -03:00
|
|
|
if (I2CD[bus.busnum].i2c->errors & I2C_ISR_LIMIT) {
|
2020-04-29 21:40:45 -03:00
|
|
|
INTERNAL_ERROR(AP_InternalError::error_t::i2c_isr);
|
2019-08-23 21:03:52 -03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-08-26 18:59:21 -03:00
|
|
|
#ifdef STM32_I2C_ISR_LIMIT
|
2019-08-25 04:46:52 -03:00
|
|
|
AP_HAL::Util::PersistentData &pd = hal.util->persistent_data;
|
|
|
|
pd.i2c_isr_count += I2CD[bus.busnum].i2c->isr_count;
|
2019-08-26 18:59:21 -03:00
|
|
|
#endif
|
2019-08-25 04:46:52 -03:00
|
|
|
|
2018-08-01 22:48:12 -03:00
|
|
|
if (ret == MSG_OK) {
|
2018-06-02 00:27:02 -03:00
|
|
|
bus.bouncebuffer_finish(send, recv, recv_len);
|
2018-02-06 02:48:10 -04:00
|
|
|
i2cReleaseBus(I2CD[bus.busnum].i2c);
|
2018-01-05 02:19:51 -04:00
|
|
|
return true;
|
|
|
|
}
|
2018-11-15 06:25:29 -04:00
|
|
|
#if HAL_I2C_CLEAR_ON_TIMEOUT
|
|
|
|
if (ret == MSG_TIMEOUT && I2CBus::read_sda(bus.busnum) == 0) {
|
|
|
|
I2CBus::clear_bus(bus.busnum);
|
|
|
|
}
|
|
|
|
#endif
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
2018-06-02 00:27:02 -03:00
|
|
|
bus.bouncebuffer_finish(send, recv, recv_len);
|
2018-02-06 02:48:10 -04:00
|
|
|
i2cReleaseBus(I2CD[bus.busnum].i2c);
|
2018-01-05 02:19:51 -04:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool I2CDevice::read_registers_multiple(uint8_t first_reg, uint8_t *recv,
|
|
|
|
uint32_t recv_len, uint8_t times)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
/*
|
|
|
|
register a periodic callback
|
|
|
|
*/
|
|
|
|
AP_HAL::Device::PeriodicHandle I2CDevice::register_periodic_callback(uint32_t period_usec, AP_HAL::Device::PeriodicCb cb)
|
|
|
|
{
|
2018-01-10 00:26:05 -04:00
|
|
|
return bus.register_periodic_callback(period_usec, cb, this);
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
2019-10-20 10:31:12 -03:00
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
|
|
|
|
/*
|
|
|
|
adjust a periodic callback
|
|
|
|
*/
|
|
|
|
bool I2CDevice::adjust_periodic_callback(AP_HAL::Device::PeriodicHandle h, uint32_t period_usec)
|
|
|
|
{
|
2018-01-10 00:26:05 -04:00
|
|
|
return bus.adjust_timer(h, period_usec);
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
AP_HAL::OwnPtr<AP_HAL::I2CDevice>
|
2018-01-10 00:26:05 -04:00
|
|
|
I2CDeviceManager::get_device(uint8_t bus, uint8_t address,
|
|
|
|
uint32_t bus_clock,
|
|
|
|
bool use_smbus,
|
|
|
|
uint32_t timeout_ms)
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2018-01-19 18:01:06 -04:00
|
|
|
bus -= HAL_I2C_BUS_BASE;
|
2018-08-02 20:27:17 -03:00
|
|
|
if (bus >= ARRAY_SIZE(I2CD)) {
|
2018-01-08 00:33:08 -04:00
|
|
|
return AP_HAL::OwnPtr<AP_HAL::I2CDevice>(nullptr);
|
|
|
|
}
|
2018-01-10 00:26:05 -04:00
|
|
|
auto dev = AP_HAL::OwnPtr<AP_HAL::I2CDevice>(new I2CDevice(bus, address, bus_clock, use_smbus, timeout_ms));
|
2018-01-05 02:19:51 -04:00
|
|
|
return dev;
|
|
|
|
}
|
2018-03-01 20:46:30 -04:00
|
|
|
|
2018-06-21 00:09:15 -03:00
|
|
|
/*
|
|
|
|
get mask of bus numbers for all configured I2C buses
|
|
|
|
*/
|
|
|
|
uint32_t I2CDeviceManager::get_bus_mask(void) const
|
|
|
|
{
|
2018-08-02 20:27:17 -03:00
|
|
|
return ((1U << ARRAY_SIZE(I2CD)) - 1) << HAL_I2C_BUS_BASE;
|
2018-06-21 00:09:15 -03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
get mask of bus numbers for all configured internal I2C buses
|
|
|
|
*/
|
|
|
|
uint32_t I2CDeviceManager::get_bus_mask_internal(void) const
|
|
|
|
{
|
|
|
|
// assume first bus is internal
|
2018-07-13 06:47:38 -03:00
|
|
|
return get_bus_mask() & HAL_I2C_INTERNAL_MASK;
|
2018-06-21 00:09:15 -03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
get mask of bus numbers for all configured external I2C buses
|
|
|
|
*/
|
|
|
|
uint32_t I2CDeviceManager::get_bus_mask_external(void) const
|
|
|
|
{
|
|
|
|
// assume first bus is internal
|
2018-07-13 06:47:38 -03:00
|
|
|
return get_bus_mask() & ~HAL_I2C_INTERNAL_MASK;
|
2018-06-21 00:09:15 -03:00
|
|
|
}
|
|
|
|
|
2018-03-01 20:46:30 -04:00
|
|
|
#endif // HAL_USE_I2C
|