2018-01-05 02:19:51 -04:00
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/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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2019-10-20 10:31:12 -03:00
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*
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2018-01-05 02:19:51 -04:00
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* Code by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <AP_HAL/AP_HAL.h>
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#include <AP_HAL/system.h>
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2019-07-16 01:45:34 -03:00
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#include <AP_BoardConfig/AP_BoardConfig.h>
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2021-02-23 19:31:32 -04:00
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#include <AP_InternalError/AP_InternalError.h>
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2019-07-16 01:45:34 -03:00
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#include "hwdef/common/watchdog.h"
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2019-11-26 00:03:05 -04:00
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#include "hwdef/common/stm32_util.h"
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2021-05-17 06:45:10 -03:00
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#include <AP_Vehicle/AP_Vehicle_Type.h>
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2022-08-15 04:22:48 -03:00
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#if AP_CRASHDUMP_ENABLED
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2021-10-23 05:08:28 -03:00
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#include <CrashCatcher.h>
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2021-10-29 08:32:03 -03:00
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#endif
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2018-01-05 02:19:51 -04:00
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#include <ch.h>
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#include "hal.h"
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#include <hrt.h>
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2019-12-08 07:49:06 -04:00
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#if CH_CFG_ST_RESOLUTION == 16
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static_assert(sizeof(systime_t) == 2, "expected 16 bit systime_t");
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#elif CH_CFG_ST_RESOLUTION == 32
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static_assert(sizeof(systime_t) == 4, "expected 32 bit systime_t");
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#endif
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2021-10-12 02:57:15 -03:00
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static_assert(sizeof(systime_t) == sizeof(sysinterval_t), "expected systime_t same size as sysinterval_t");
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2019-12-08 07:49:06 -04:00
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2020-05-06 23:13:29 -03:00
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#if defined(HAL_EXPECTED_SYSCLOCK)
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#ifdef STM32_SYS_CK
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static_assert(HAL_EXPECTED_SYSCLOCK == STM32_SYS_CK, "unexpected STM32_SYS_CK value");
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#elif defined(STM32_HCLK)
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static_assert(HAL_EXPECTED_SYSCLOCK == STM32_HCLK, "unexpected STM32_HCLK value");
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#else
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#error "unknown system clock"
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#endif
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#endif
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2023-02-25 01:03:27 -04:00
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// debug variables chew up flash, but are handy if you've got a Fault and need
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// easy access to the fault data iun the debugger:
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#ifndef AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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#define AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED 1
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#endif
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2023-01-30 12:18:13 -04:00
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#define QUOTE(str) #str
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#define EXPAND_AND_QUOTE(str) QUOTE(str)
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#define ASSERT_CLOCK(clk) static_assert(HAL_EXPECTED_ ##clk == (clk), "unexpected " #clk " value: '" EXPAND_AND_QUOTE(clk) "'")
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#if defined(HAL_EXPECTED_STM32_SYS_CK) && defined(STM32_SYS_CK)
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ASSERT_CLOCK(STM32_SYS_CK);
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#endif
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#if defined(HAL_EXPECTED_STM32_HCLK) && defined(STM32_HCLK)
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ASSERT_CLOCK(STM32_HCLK);
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#endif
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#if defined(HAL_EXPECTED_STM32_SDMMC1CLK) && defined(STM32_SDMMC1CLK)
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ASSERT_CLOCK(STM32_SDMMC1CLK);
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#endif
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#if defined(HAL_EXPECTED_STM32_SPI45CLK) && defined(STM32_SPI45CLK)
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ASSERT_CLOCK(STM32_SPI45CLK);
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#endif
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#if defined(HAL_EXPECTED_STM32_FDCANCLK) && defined(STM32_FDCANCLK)
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ASSERT_CLOCK(STM32_FDCANCLK);
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#endif
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2018-01-05 02:19:51 -04:00
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extern const AP_HAL::HAL& hal;
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extern "C"
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{
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#define bkpt() __asm volatile("BKPT #0\n")
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2022-08-15 04:22:48 -03:00
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#if !AP_CRASHDUMP_ENABLED
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2021-10-29 08:32:03 -03:00
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// do legacy hardfault handling
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void HardFault_Handler(void);
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void HardFault_Handler(void) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx));
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(void)ctx;
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//For HardFault/BusFault this is the address that was accessed causing the error
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uint32_t faultAddress = SCB->BFAR;
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(void)faultAddress;
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2023-02-25 01:03:27 -04:00
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#if AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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2021-10-29 08:32:03 -03:00
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bool forced = SCB->HFSR & SCB_HFSR_FORCED_Msk;
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(void)forced;
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uint32_t cfsr = SCB->CFSR;
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(void)cfsr;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false);
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bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false);
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bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false);
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(void)isFaultPrecise;
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(void)isFaultImprecise;
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(void)isFaultOnUnstacking;
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(void)isFaultOnStacking;
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(void)isFaultAddressValid;
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2023-02-25 01:03:27 -04:00
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#endif // #if AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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2021-10-29 08:32:03 -03:00
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2023-02-17 00:00:27 -04:00
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#if AP_WATCHDOG_SAVE_FAULT_ENABLED
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2021-10-29 08:32:03 -03:00
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save_fault_watchdog(__LINE__, faultType, faultAddress, (uint32_t)ctx.lr_thd);
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2023-02-17 00:00:27 -04:00
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#endif
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2021-10-29 08:32:03 -03:00
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#ifdef HAL_GPIO_PIN_FAULT
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while (true) {
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// forced means that another kind of unhandled fault got escalated to a hardfault
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if (faultType == BusFault) {
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fault_printf("BUSFAULT\n");
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} else if (forced) {
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fault_printf("FORCED HARDFAULT\n");
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} else {
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fault_printf("HARDFAULT(%d)\n", int(faultType));
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}
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fault_printf("CSFR=0x%08x\n", cfsr);
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2022-11-10 12:49:54 -04:00
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fault_printf("CUR=0x%08x\n", currcore->rlist.current);
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if (currcore->rlist.current) {
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fault_printf("NAME=%s\n", currcore->rlist.current->name);
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2021-10-29 08:32:03 -03:00
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}
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fault_printf("FA=0x%08x\n", faultAddress);
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fault_printf("PC=0x%08x\n", ctx.pc);
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fault_printf("LR=0x%08x\n", ctx.lr_thd);
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fault_printf("R0=0x%08x\n", ctx.r0);
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fault_printf("R1=0x%08x\n", ctx.r1);
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fault_printf("R2=0x%08x\n", ctx.r2);
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fault_printf("R3=0x%08x\n", ctx.r3);
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fault_printf("R12=0x%08x\n", ctx.r12);
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fault_printf("XPSR=0x%08x\n", ctx.xpsr);
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fault_printf("\n\n");
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}
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#endif
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//Cause debugger to stop. Ignored if no debugger is attached
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while(1) {}
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}
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// For the BusFault handler to be active SCB_SHCSR_BUSFAULTENA_Msk should be set in SCB->SHCSR
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// ChibiOS does not do this by default
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void BusFault_Handler(void) __attribute__((alias("HardFault_Handler")));
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void UsageFault_Handler(void);
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void UsageFault_Handler(void) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx));
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(void)ctx;
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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uint32_t faultAddress = SCB->BFAR;
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2023-02-17 00:00:27 -04:00
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(void)faultAddress;
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2023-02-25 01:03:27 -04:00
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#if AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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2021-10-29 08:32:03 -03:00
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false);
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bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false);
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bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false);
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bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false);
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(void)isUndefinedInstructionFault;
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(void)isEPSRUsageFault;
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(void)isInvalidPCFault;
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(void)isNoCoprocessorFault;
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(void)isUnalignedAccessFault;
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(void)isDivideByZeroFault;
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2023-02-25 01:03:27 -04:00
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#endif // AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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2021-10-29 08:32:03 -03:00
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2023-02-17 00:00:27 -04:00
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#if AP_WATCHDOG_SAVE_FAULT_ENABLED
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2021-10-29 08:32:03 -03:00
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save_fault_watchdog(__LINE__, faultType, faultAddress, (uint32_t)ctx.lr_thd);
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2023-02-17 00:00:27 -04:00
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#endif
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2021-10-29 08:32:03 -03:00
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//Cause debugger to stop. Ignored if no debugger is attached
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while(1) {}
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}
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void MemManage_Handler(void);
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void MemManage_Handler(void) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx));
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(void)ctx;
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//For HardFault/BusFault this is the address that was accessed causing the error
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uint32_t faultAddress = SCB->MMFAR;
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(void)faultAddress;
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2023-02-17 00:00:27 -04:00
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#if AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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2021-10-29 08:32:03 -03:00
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false);
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bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false);
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bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false);
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(void)isInstructionAccessViolation;
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(void)isDataAccessViolation;
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(void)isExceptionUnstackingFault;
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(void)isExceptionStackingFault;
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(void)isFaultAddressValid;
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2023-02-25 01:03:27 -04:00
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#endif // AP_FAULTHANDLER_DEBUG_VARIABLES_ENABLED
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2021-10-29 08:32:03 -03:00
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2023-02-17 00:00:27 -04:00
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#if AP_WATCHDOG_SAVE_FAULT_ENABLED
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2021-10-29 08:32:03 -03:00
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save_fault_watchdog(__LINE__, faultType, faultAddress, (uint32_t)ctx.lr_thd);
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2023-02-17 00:00:27 -04:00
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#endif
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2021-10-29 08:32:03 -03:00
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while(1) {}
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}
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#else
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// Handle via Crash Catcher
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extern void HardFault_Handler(void);
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void BusFault_Handler(void);
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void BusFault_Handler(void) {
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HardFault_Handler();
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}
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void UsageFault_Handler(void);
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void UsageFault_Handler(void) {
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HardFault_Handler();
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}
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void MemManage_Handler(void);
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void MemManage_Handler(void) {
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HardFault_Handler();
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}
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#endif
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2023-02-17 00:00:27 -04:00
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#if AP_WATCHDOG_SAVE_FAULT_ENABLED
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2019-07-16 01:45:34 -03:00
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/*
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save watchdog data for a hard fault
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*/
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2021-10-23 05:08:28 -03:00
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void save_fault_watchdog(uint16_t line, FaultType fault_type, uint32_t fault_addr, uint32_t lr)
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2019-07-16 01:45:34 -03:00
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{
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bool using_watchdog = AP_BoardConfig::watchdog_enabled();
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if (using_watchdog) {
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AP_HAL::Util::PersistentData &pd = hal.util->persistent_data;
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2020-04-28 03:34:52 -03:00
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if (pd.fault_type == 0) {
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// don't overwrite earlier fault
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2021-01-25 17:16:46 -04:00
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pd.fault_line = line;
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2020-04-28 03:34:52 -03:00
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pd.fault_type = fault_type;
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2021-01-25 17:16:46 -04:00
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pd.fault_addr = fault_addr;
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thread_t *tp = chThdGetSelfX();
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if (tp) {
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2021-02-18 17:52:58 -04:00
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pd.fault_thd_prio = tp->hdr.pqueue.prio;
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2021-01-25 17:16:46 -04:00
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// get first 4 bytes of the name, but only of first fault
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if (tp->name && pd.thread_name4[0] == 0) {
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strncpy_noterm(pd.thread_name4, tp->name, 4);
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}
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2020-04-28 03:34:52 -03:00
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|
}
|
2021-01-25 17:16:46 -04:00
|
|
|
pd.fault_icsr = SCB->ICSR;
|
|
|
|
pd.fault_lr = lr;
|
2020-04-28 03:34:52 -03:00
|
|
|
}
|
2019-07-16 01:45:34 -03:00
|
|
|
stm32_watchdog_save((uint32_t *)&hal.util->persistent_data, (sizeof(hal.util->persistent_data)+3)/4);
|
|
|
|
}
|
|
|
|
}
|
2023-02-17 00:00:27 -04:00
|
|
|
#endif // AP_WATCHDOG_SAVE_FAULT_ENABLED
|
2019-07-16 01:45:34 -03:00
|
|
|
|
2021-10-23 05:08:28 -03:00
|
|
|
void *__dso_handle;
|
2019-07-16 01:45:34 -03:00
|
|
|
|
2021-10-23 05:08:28 -03:00
|
|
|
void __cxa_pure_virtual(void);
|
|
|
|
void __cxa_pure_virtual() { while (1); } //TODO: Handle properly, maybe generate a traceback
|
2019-07-16 01:45:34 -03:00
|
|
|
|
2021-10-23 05:08:28 -03:00
|
|
|
void NMI_Handler(void);
|
|
|
|
void NMI_Handler(void) { while (1); }
|
2019-07-16 01:45:34 -03:00
|
|
|
|
2022-08-16 00:10:27 -03:00
|
|
|
#if defined(HAL_BOOTLOADER_BUILD) && HAL_ENABLE_DFU_BOOT
|
|
|
|
void __entry_hook(void);
|
|
|
|
void __entry_hook()
|
|
|
|
{
|
|
|
|
// read the persistent data
|
|
|
|
AP_HAL::Util::PersistentData pd;
|
|
|
|
stm32_watchdog_load((uint32_t *)&pd, (sizeof(pd)+3)/4);
|
|
|
|
if (pd.boot_to_dfu) {
|
|
|
|
pd.boot_to_dfu = false;
|
|
|
|
stm32_watchdog_save((uint32_t *)&pd, (sizeof(pd)+3)/4);
|
|
|
|
#if defined(STM32H7)
|
|
|
|
const uint32_t *app_base = (const uint32_t *)(0x1FF09800);
|
|
|
|
#else
|
|
|
|
const uint32_t *app_base = (const uint32_t *)(0x1FFF0000);
|
|
|
|
#endif
|
|
|
|
__set_MSP(*app_base);
|
|
|
|
((void (*)())*(&app_base[1]))();
|
|
|
|
while(true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
namespace AP_HAL {
|
|
|
|
|
|
|
|
void init()
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void panic(const char *errormsg, ...)
|
|
|
|
{
|
2021-05-17 06:45:10 -03:00
|
|
|
#if !defined(HAL_BOOTLOADER_BUILD) && !APM_BUILD_TYPE(APM_BUILD_iofirmware)
|
2021-02-23 19:31:32 -04:00
|
|
|
INTERNAL_ERROR(AP_InternalError::error_t::panic);
|
2018-01-05 02:19:51 -04:00
|
|
|
va_list ap;
|
|
|
|
|
|
|
|
va_start(ap, errormsg);
|
|
|
|
vprintf(errormsg, ap);
|
|
|
|
va_end(ap);
|
|
|
|
|
|
|
|
hal.scheduler->delay_microseconds(10000);
|
2019-12-26 20:45:03 -04:00
|
|
|
while (1) {
|
2021-01-04 02:02:35 -04:00
|
|
|
va_start(ap, errormsg);
|
2019-12-26 20:45:03 -04:00
|
|
|
vprintf(errormsg, ap);
|
2021-01-04 02:02:35 -04:00
|
|
|
va_end(ap);
|
2019-12-26 20:45:03 -04:00
|
|
|
hal.scheduler->delay(500);
|
|
|
|
}
|
2020-07-30 14:50:57 -03:00
|
|
|
#else
|
|
|
|
// we don't support variable args in bootlaoder
|
|
|
|
chSysHalt(errormsg);
|
|
|
|
// we will never get here, this just to silence a warning
|
|
|
|
while (1) {}
|
|
|
|
#endif
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint32_t micros()
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2021-10-02 01:55:20 -03:00
|
|
|
#if CH_CFG_ST_RESOLUTION == 32 && CH_CFG_ST_FREQUENCY==1000000U
|
|
|
|
// special case optimisation for 32 bit timers
|
2023-03-23 04:39:23 -03:00
|
|
|
#ifdef AP_BOARD_START_TIME
|
|
|
|
return st_lld_get_counter() + AP_BOARD_START_TIME;
|
|
|
|
#else
|
2021-10-02 01:55:20 -03:00
|
|
|
return st_lld_get_counter();
|
2023-03-23 04:39:23 -03:00
|
|
|
#endif
|
2021-10-02 01:55:20 -03:00
|
|
|
#else
|
2018-08-08 03:57:05 -03:00
|
|
|
return hrt_micros32();
|
2021-10-02 01:55:20 -03:00
|
|
|
#endif
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2021-10-02 02:39:30 -03:00
|
|
|
uint16_t micros16()
|
|
|
|
{
|
|
|
|
#if CH_CFG_ST_RESOLUTION == 32 && CH_CFG_ST_FREQUENCY==1000000U
|
|
|
|
return st_lld_get_counter() & 0xFFFF;
|
|
|
|
#elif CH_CFG_ST_RESOLUTION == 16 && CH_CFG_ST_FREQUENCY==1000000U
|
|
|
|
return st_lld_get_counter();
|
|
|
|
#else
|
|
|
|
return hrt_micros32() & 0xFFFF;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint32_t millis()
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2018-08-08 03:57:05 -03:00
|
|
|
return hrt_millis32();
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint16_t millis16()
|
2018-08-08 01:56:28 -03:00
|
|
|
{
|
|
|
|
return hrt_millis32() & 0xFFFF;
|
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint64_t micros64()
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2018-08-08 03:57:05 -03:00
|
|
|
return hrt_micros64();
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint64_t millis64()
|
2018-01-05 02:19:51 -04:00
|
|
|
{
|
2018-08-08 03:57:05 -03:00
|
|
|
return hrt_micros64() / 1000U;
|
2018-01-05 02:19:51 -04:00
|
|
|
}
|
|
|
|
|
2020-08-09 07:35:38 -03:00
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint32_t native_micros()
|
2020-08-09 07:35:38 -03:00
|
|
|
{
|
|
|
|
return micros();
|
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint32_t native_millis()
|
2020-08-09 07:35:38 -03:00
|
|
|
{
|
|
|
|
return millis();
|
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint16_t native_millis16()
|
2020-08-09 07:35:38 -03:00
|
|
|
{
|
|
|
|
return millis16();
|
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint64_t native_micros64()
|
2020-08-09 07:35:38 -03:00
|
|
|
{
|
|
|
|
return micros64();
|
|
|
|
}
|
|
|
|
|
2021-09-04 08:59:15 -03:00
|
|
|
__FASTRAMFUNC__ uint64_t native_millis64()
|
2020-08-09 07:35:38 -03:00
|
|
|
{
|
|
|
|
return millis64();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
} // namespace AP_HAL
|