48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
#ifndef MT9M021_H
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#define MT9M021_H
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struct v4l2_subdev;
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/*
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* struct mt9m021_platform_data - MT9M021 platform data
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* @reset: Chip reset GPIO (set to -1 if not used)
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* @ext_freq: Input clock frequency
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* @target_freq: Pixel clock frequency
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*/
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static uint16_t mt9m021_seq_data[] = {
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0x3227, 0x0101, 0x0F25, 0x0808, 0x0227, 0x0101, 0x0837, 0x2700,
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0x0138, 0x2701, 0x013A, 0x2700, 0x0125, 0x0020, 0x3C25, 0x0040,
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0x3427, 0x003F, 0x2500, 0x2037, 0x2540, 0x4036, 0x2500, 0x4031,
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0x2540, 0x403D, 0x6425, 0x2020, 0x3D64, 0x2510, 0x1037, 0x2520,
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0x2010, 0x2510, 0x100F, 0x2708, 0x0802, 0x2540, 0x402D, 0x2608,
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0x280D, 0x1709, 0x2600, 0x2805, 0x26A7, 0x2807, 0x2580, 0x8029,
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0x1705, 0x2500, 0x4027, 0x2222, 0x1616, 0x2726, 0x2617, 0x3626,
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0xA617, 0x0326, 0xA417, 0x1F28, 0x0526, 0x2028, 0x0425, 0x2020,
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0x2700, 0x2625, 0x0000, 0x171E, 0x2500, 0x0425, 0x0020, 0x2117,
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0x121B, 0x1703, 0x2726, 0x2617, 0x2828, 0x0517, 0x1A26, 0x6017,
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0xAE25, 0x0080, 0x2700, 0x2626, 0x1828, 0x002E, 0x2A28, 0x081E,
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0x4127, 0x1010, 0x0214, 0x6060, 0x0A14, 0x6060, 0x0B14, 0x6060,
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0x0C14, 0x6060, 0x0D14, 0x6060, 0x0217, 0x3C14, 0x0060, 0x0A14,
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0x0060, 0x0B14, 0x0060, 0x0C14, 0x0060, 0x0D14, 0x0060, 0x0811,
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0x2500, 0x1027, 0x0010, 0x2F6F, 0x0F3E, 0x2500, 0x0827, 0x0008,
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0x3066, 0x3225, 0x0008, 0x2700, 0x0830, 0x6631, 0x3D64, 0x2508,
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0x083D, 0xFF3D, 0x2A27, 0x083F, 0x2C00
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};
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static uint16_t mt9m021_analog_setting[] = {
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0x00FD, 0x0FFF, 0x0003, 0xF87A, 0xE075, 0x077C, 0xA4EB, 0xD208
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};
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/***************************************************
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NVIDIA Camera Common Defines
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****************************************************/
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enum mt9m021_modes{
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MT9M021_DEFAULT_MODE
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};
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static const int mt9m021_framerates[] = {10, 20, 30, 40, 50, 60,};
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#endif
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