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base: dchvs:6f6cbd2465f2b4c963a0addeccb24ce1247d1b0f
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dchvs:master
dchvs:feature/resolution-1280x960
dchvs:jetpack-4.4.1
dchvs:hotfix/fix-low-framerate
dchvs:jetpack-4.2.2
dchvs:v0.2.6
dchvs:v0.2.5
dchvs:v0.2.4
dchvs:v0.2.3
dchvs:v0.2.2
dchvs:v0.2.1
dchvs:v0.2.0
dchvs:v0.1.0
...
compare: dchvs:712fc2f18b09b5205a282eaa3e23e3e1f115e12e
Branches Tags
dchvs:master
dchvs:feature/resolution-1280x960
dchvs:jetpack-4.4.1
dchvs:hotfix/fix-low-framerate
dchvs:jetpack-4.2.2
dchvs:v0.2.6
dchvs:v0.2.5
dchvs:v0.2.4
dchvs:v0.2.3
dchvs:v0.2.2
dchvs:v0.2.1
dchvs:v0.2.0
dchvs:v0.1.0

2 Commits
6f6cbd2465 ... 712fc2f18b

Author SHA1 Message Date
dchvs 712fc2f18b Set gain to range 102-160 in order to not have dotted image and blinking 2021-03-29 12:18:11 -06:00
dchvs 855ce6a4d5 Fix identation 2021-03-29 09:33:30 -06:00
3 changed files with 218 additions and 219 deletions
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16
hardware/nvidia-spiri/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-tx2-spiri-camera.dtsi
View File

@ -102,7 +102,7 @@ i2c8 = "/i2c@31e0000";
framerate_factor = "1000000"; framerate_factor = "1000000";
exposure_factor = "1000000"; exposure_factor = "1000000";
min_gain_val = "102"; min_gain_val = "102";
max_gain_val = "250"; max_gain_val = "160";
step_gain_val = "1"; step_gain_val = "1";
default_gain = "102"; default_gain = "102";
min_hdr_ratio = "1"; min_hdr_ratio = "1";
@ -116,7 +116,7 @@ i2c8 = "/i2c@31e0000";
min_exp_time = "100"; // us min_exp_time = "100"; // us
max_exp_time = "16620"; // us max_exp_time = "16620"; // us
step_exp_time = "1"; step_exp_time = "1";
default_exp_time = "15000"; // us default_exp_time = "16620"; // us
}; };
mode1 { mode1 {
mclk_khz = "24000"; mclk_khz = "24000";
@ -141,7 +141,7 @@ i2c8 = "/i2c@31e0000";
framerate_factor = "1000000"; framerate_factor = "1000000";
exposure_factor = "1000000"; exposure_factor = "1000000";
min_gain_val = "102"; min_gain_val = "102";
max_gain_val = "250"; max_gain_val = "160";
step_gain_val = "1"; step_gain_val = "1";
default_gain = "102"; default_gain = "102";
min_hdr_ratio = "1"; min_hdr_ratio = "1";
@ -155,7 +155,7 @@ i2c8 = "/i2c@31e0000";
min_exp_time = "100"; // us min_exp_time = "100"; // us
max_exp_time = "22220"; // us max_exp_time = "22220"; // us
step_exp_time = "1"; step_exp_time = "1";
default_exp_time = "15000"; // us default_exp_time = "22220"; // us
}; };
ports { ports {
@ -229,7 +229,7 @@ i2c8 = "/i2c@31e0000";
framerate_factor = "1000000"; framerate_factor = "1000000";
exposure_factor = "1000000"; exposure_factor = "1000000";
min_gain_val = "102"; min_gain_val = "102";
max_gain_val = "250" ; max_gain_val = "160" ;
step_gain_val = "1"; step_gain_val = "1";
default_gain = "102"; default_gain = "102";
min_hdr_ratio = "1"; min_hdr_ratio = "1";
@ -243,7 +243,7 @@ i2c8 = "/i2c@31e0000";
min_exp_time = "100"; // us min_exp_time = "100"; // us
max_exp_time = "16620"; // us max_exp_time = "16620"; // us
step_exp_time = "1"; step_exp_time = "1";
default_exp_time = "15000"; // us default_exp_time = "16620"; // us
}; };
mode1 { mode1 {
mclk_khz = "24000"; mclk_khz = "24000";
@ -268,7 +268,7 @@ i2c8 = "/i2c@31e0000";
framerate_factor = "1000000"; framerate_factor = "1000000";
exposure_factor = "1000000"; exposure_factor = "1000000";
min_gain_val = "102"; min_gain_val = "102";
max_gain_val = "250"; max_gain_val = "160";
step_gain_val = "1"; step_gain_val = "1";
default_gain = "102"; default_gain = "102";
min_hdr_ratio = "1"; min_hdr_ratio = "1";
@ -282,7 +282,7 @@ i2c8 = "/i2c@31e0000";
min_exp_time = "100"; // us min_exp_time = "100"; // us
max_exp_time = "22220"; // us max_exp_time = "22220"; // us
step_exp_time = "1"; step_exp_time = "1";
default_exp_time = "15000"; // us default_exp_time = "22220"; // us
}; };
ports { ports {
#address-cells = <0x1>; #address-cells = <0x1>;

41
kernel/nvidia-spiri/drivers/media/i2c/mt9m021.c
View File

@ -442,18 +442,16 @@ static int mt9m021_set_gain(struct tegracam_device *tc_dev, s64 val)
goto exit; goto exit;
/* Update global gain */ /* Update global gain */
err = err = mt9m021_write_reg16(s_data, MT9M021_GLOBAL_GAIN, gain);
mt9m021_write_reg16(s_data, MT9M021_GLOBAL_GAIN, gain);
if (err) if (err)
goto exit; goto exit;
err = err = mt9m021_write_reg16(s_data, MT9M021_GLOBAL_GAIN_CB, gain);
mt9m021_write_reg16(s_data, MT9M021_GLOBAL_GAIN_CB, gain);
if (err) if (err)
goto exit; goto exit;
return 0; return 0;
exit: exit:
dev_err(dev, "Gain control error: %d", err); dev_err(dev, "Gain control error: %d", err);
return err; return err;
@ -498,7 +496,7 @@ static int mt9m021_set_frame_rate(struct tegracam_device *tc_dev, s64 val)
return 0; return 0;
exit: exit:
dev_err(dev, "Frame rate control error: %d", err); dev_err(dev, "Frame rate control error: %d", err);
return err; return err;
} }
@ -544,7 +542,7 @@ static int mt9m021_set_exposure(struct tegracam_device *tc_dev, s64 val)
return err; return err;
exit: exit:
dev_err(dev, "Exposure control error: %d", err); dev_err(dev, "Exposure control error: %d", err);
return err; return err;
} }
@ -564,15 +562,14 @@ static int mt9m021_set_analog_gain(struct tegracam_device *tc_dev, s64 val)
goto exit; goto exit;
reg16 = reg16 =
(reg16 & ~MT9M021_ANALOG_GAIN_MASK) | (reg16 & ~MT9M021_ANALOG_GAIN_MASK) |
((val << MT9M021_ANALOG_GAIN_SHIFT) & ((val << MT9M021_ANALOG_GAIN_SHIFT) & MT9M021_ANALOG_GAIN_MASK);
MT9M021_ANALOG_GAIN_MASK);
err = mt9m021_write_reg16(s_data, MT9M021_DIGITAL_TEST, reg16); err = mt9m021_write_reg16(s_data, MT9M021_DIGITAL_TEST, reg16);
if (err) if (err)
goto exit; goto exit;
return 0; return 0;
exit: exit:
dev_err(dev, "Analog Gain control error: %d", err); dev_err(dev, "Analog Gain control error: %d", err);
return err; return err;
@ -625,7 +622,7 @@ static int mt9m021_set_digital_gain(struct tegracam_device *tc_dev, s64 val,
return 0; return 0;
exit: exit:
dev_err(dev, "Digital Gain control error: %d", err); dev_err(dev, "Digital Gain control error: %d", err);
return err; return err;
} }
@ -642,14 +639,13 @@ static int mt9m021_set_test_pattern(struct tegracam_device *tc_dev, s32 val)
err = mt9m021_write_reg16(s_data, MT9M021_TEST_PATTERN, err = mt9m021_write_reg16(s_data, MT9M021_TEST_PATTERN,
MT9M021_TEST_PATTERN_VAL); MT9M021_TEST_PATTERN_VAL);
else else
err = mt9m021_write_reg16(s_data, MT9M021_TEST_PATTERN, err = mt9m021_write_reg16(s_data, MT9M021_TEST_PATTERN, val);
val);
if (err) if (err)
goto exit; goto exit;
return 0; return 0;
exit: exit:
dev_err(dev, "Test Pattern control error: %d", err); dev_err(dev, "Test Pattern control error: %d", err);
return err; return err;
@ -664,7 +660,7 @@ static int mt9m021_set_flash(struct tegracam_device *tc_dev, s32 val)
dev_dbg(dev, "Setting Flash to: %d", val); dev_dbg(dev, "Setting Flash to: %d", val);
switch(val) { switch (val) {
case V4L2_FLASH_LED_MODE_NONE: case V4L2_FLASH_LED_MODE_NONE:
err = mt9m021_write_reg16(s_data, MT9M021_FLASH, 0x0000); err = mt9m021_write_reg16(s_data, MT9M021_FLASH, 0x0000);
priv->flash_en = false; priv->flash_en = false;
@ -683,7 +679,7 @@ static int mt9m021_set_flash(struct tegracam_device *tc_dev, s32 val)
goto exit; goto exit;
return 0; return 0;
exit: exit:
dev_err(dev, "Flash control error: %d", err); dev_err(dev, "Flash control error: %d", err);
return err; return err;
@ -697,7 +693,7 @@ static int mt9m021_set_flip(struct tegracam_device *tc_dev, s32 val, int id)
dev_dbg(dev, "Setting Flip to: %d", val); dev_dbg(dev, "Setting Flip to: %d", val);
switch(id) { switch (id) {
case V4L2_CID_HFLIP: case V4L2_CID_HFLIP:
err = mt9m021_update_bits(s_data, MT9M021_READ_MODE, err = mt9m021_update_bits(s_data, MT9M021_READ_MODE,
val << 14, MT9M021_HFLIP_MASK); val << 14, MT9M021_HFLIP_MASK);
@ -716,7 +712,7 @@ static int mt9m021_set_flip(struct tegracam_device *tc_dev, s32 val, int id)
goto exit; goto exit;
return 0; return 0;
exit: exit:
dev_err(dev, "Flip control error: %d", err); dev_err(dev, "Flip control error: %d", err);
return err; return err;
@ -787,7 +783,7 @@ static int mt9m021_power_off(struct camera_common_data *s_data)
usleep_range(2000, 2010); usleep_range(2000, 2010);
} }
power_off_done: power_off_done:
pw->state = SWITCH_OFF; pw->state = SWITCH_OFF;
return 0; return 0;
@ -909,7 +905,7 @@ static struct camera_common_pdata *mt9m021_parse_dt(struct tegracam_device
return board_priv_pdata; return board_priv_pdata;
error: error:
devm_kfree(dev, board_priv_pdata); devm_kfree(dev, board_priv_pdata);
return ret; return ret;
@ -1116,7 +1112,8 @@ static int mt9m021_verify_chip_id(struct mt9m021 *priv)
err = mt9m021_read_reg16(s_data, MT9M021_CHIP_ID_REG, &chip_id); err = mt9m021_read_reg16(s_data, MT9M021_CHIP_ID_REG, &chip_id);
if (!err) if (!err)
break; break;
dev_info(&client->dev, "Failed to read Chip ID, trying again\n"); dev_info(&client->dev,
"Failed to read Chip ID, trying again\n");
max_retries--; max_retries--;
msleep(30); msleep(30);
} }
@ -1132,7 +1129,7 @@ static int mt9m021_verify_chip_id(struct mt9m021 *priv)
goto exit; goto exit;
} }
exit: exit:
ret = mt9m021_power_off(s_data); ret = mt9m021_power_off(s_data);
if (ret) if (ret)
return ret; return ret;

6
kernel/nvidia-spiri/drivers/media/i2c/mt9m021_mode_tbls.h
View File

@ -173,8 +173,10 @@ static const int mt9m021_framerates_1280x960[] = {
}; };
static const struct camera_common_frmfmt mt9m021_frmfmt[] = { static const struct camera_common_frmfmt mt9m021_frmfmt[] = {
{{1280, 720}, mt9m021_framerates_1280x720, 1, 0, MT9M021_MODE_1280x720_60FPS}, {{1280, 720}, mt9m021_framerates_1280x720, 1, 0,
{{1280, 960}, mt9m021_framerates_1280x960, 1, 0, MT9M021_MODE_1280x960_45FPS}, MT9M021_MODE_1280x720_60FPS},
{{1280, 960}, mt9m021_framerates_1280x960, 1, 0,
MT9M021_MODE_1280x960_45FPS},
}; };
#endif /* __MT9M021_I2C_TABLES__ */ #endif /* __MT9M021_I2C_TABLES__ */